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Improved Core Isolation and Access for Hierarchical Embedded Test
January/February 2009 (vol. 26 no. 1)
pp. 18-25
ASCII Text
x 
 
Benoit Nadeau-Dostie, Saman M.I. Adham, Russell Abbott, "Improved Core Isolation and Access for Hierarchical Embedded Test," IEEE Design & Test of Computers, vol. 26, no. 1, pp. 18-25, January/February, 2009.
 
 
BibTex
x
 
@article{ 10.1109/MDT.2009.13,
author = {Benoit Nadeau-Dostie and Saman M.I. Adham and Russell Abbott},
title = {Improved Core Isolation and Access for Hierarchical Embedded Test},
journal ={IEEE Design & Test of Computers},
volume = {26},
number = {1},
issn = {0740-7475},
year = {2009},
pages = {18-25},
doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2009.13},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - MGZN
JO - IEEE Design & Test of Computers
TI - Improved Core Isolation and Access for Hierarchical Embedded Test
IS - 1
SN - 0740-7475
SP18
EP25
EPD - 18-25
A1 - Benoit Nadeau-Dostie,
A1 - Saman M.I. Adham,
A1 - Russell Abbott,
PY - 2009
KW - hierarchical test
KW - embedded test
KW - IEEE Std 1500
KW - core isolation
KW - shared isolation
KW - WSP
KW - TAP
VL - 26
JA - IEEE Design & Test of Computers
ER -
 
Benoit Nadeau-Dostie, LogicVision
Saman M.I. Adham, LogicVision
Russell Abbott, LogicVision
IEEE Std 1500 enables automation and hence allows for easier and faster integration of embedded cores into an SoC. This article describes an automated test development system based on the concept of embedded test.

1. IEEE Std 1149.1-2001, Standard Test Access Port and Boundary Scan Architecture, IEEE, 2001.
2. Y. Zorian, E.J. Marinissen, and S. Dey, "Testing Embedded-Core Based System Chips," Proc. Int'l Test Conf. (ITC 98), IEEE CS Press, 1998, pp. 130-143.
3. R.K. Gupta and Y. Zorian, "Introducing Core-Based System Design," IEEE Design and Test, vol. 14, no. 4, Oct.-Dec. 1997, pp. 15-25.
4. J.-F. Côté and B. Nadeau-Dostie, Test Access Circuit and Method of Accessing Embedded Test Controllers in Integrated Circuit Modules, US patent 6,760,874, to Logic Vision Inc., Patent and Trademark Office, 2004.
5. B. Nadeau-Dostie et al., "Hierarchical Design and Test Method and System, Program Product Embodying the Method and Integrated Circuit Produced Thereby," US patent 6,615,392, to LogicVision Inc., Patent and Trademark Office, 2003.
6. IEEE Std 1500-2007, Standard Testability Method for Embedded Core-Based Integrated Circuits, IEEE, 2007.
7. B. Nadeau-Dostie ed., Design for At-Speed Test, Diagnosis and Measurement, Kluwer Academic, 2000.
8. S. Pateras, "Achieving At-Speed Structural Test," IEEE Design &Test, vol. 20, no. 5, 2003, pp. 26-33.

Index Terms:
hierarchical test, embedded test, IEEE Std 1500, core isolation, shared isolation, WSP, TAP
Citation:
Benoit Nadeau-Dostie, Saman M.I. Adham, Russell Abbott, "Improved Core Isolation and Access for Hierarchical Embedded Test," IEEE Design & Test of Computers, vol. 26, no. 1, pp. 18-25, Jan.-Feb. 2009, doi:10.1109/MDT.2009.13
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