The Community for Technology Leaders
RSS Icon
Subscribe
Issue No.01 - January/February (2009 vol.26)
pp: 8-17
Yervant Zorian , Virage Logic
ABSTRACT
IEEE Std 1500 enables modular SoC testing, not only for core-based testing, but also for divide-and-conquer test generation and test reuse. This article provides a brief tutorial on the standard and illustrates its usage through two application case studies.
INDEX TERMS
IEEE Std 1500, SoC, manufacturing test, modular testing, wrapper, test access mechanism
CITATION
Erik Jan Marinissen, Yervant Zorian, "IEEE Std 1500 Enables Modular SoC Testing", IEEE Design & Test of Computers, vol.26, no. 1, pp. 8-17, January/February 2009, doi:10.1109/MDT.2009.12
REFERENCES
1. T. McLaurin and R. Kapur, "'Wrap' Your Cores to Enable SoC Test," EE Design,24 Nov. 2004, http://www.eetimes. com/news/design/features/showArticle.jhtml?articleID=54200629.
2. A. Sehgal, J. Fitzgerald, and J. Rearick, "Test Cost Reduction for the AMD Athlon Processor Using Test Partitioning," Proc. Int'l Test Conf. (ITC 07), IEEE CS Press, 2007, paper 1.3.
3. O. Sinanoglu and E.J. Marinissen, "Analysis of the Test Data Volume Reduction Benefit of Modular SOC Testing," Proc. Design, Automation and Test in Europe Conf. (DATE 08), IEEE CS Press, 2008, pp. 182-187.
4. S. Makar et al., "Testing of Vega2, a Chip Multi-Processor with Spare Processors," Proc. Int'l Test Conf. (ITC 07), IEEE CS Press, 2007, paper 9.1.
5. Y. Zorian, E.J. Marinissen, and S. Dey, "Testing Embedded-Core Based System Chips," Proc. Int'l Test Conf. (ITC 98), IEEE CS Press, 2008, pp. 130-143.
6. S.K. Goel and E.J. Marinissen, "SOC Test Architecture Design for Efficient Utilization of Test Bandwidth," ACM Trans. Design Automation of Electronic Systems, vol. 8, no. 4, Oct. 2003, pp. 399-429.
7. E. Cota et al., "Power-Aware NoC Reuse on the Testing of Core-Based Systems," Proc. Int'l Test Conf. (ITC 03), IEEE CS Press, 2003, pp. 612-621.
8. T. Taylor and G. Maston, "Standard Test Interface Language (STIL): A New Language for Patterns and Waveforms," Proc. Int'l Test Conf. (ITC 96), IEEE CS Press, 2006, pp. 565-570.
9. IEEE Std 1450-1999, IEEE Standard Test Interface Language (STIL) for Digital Test Vector Data, IEEE, 1999.
10. E.J. Marinissen et al., "On IEEE P1500's Standard for Embedded Core Test," J. Electronic Testing: Theory and Applications, vol. 18, no. 4/5, Aug. 2002, pp. 365-383.
11. S.K. Goel et al., "Test Infrastructure Design for the Nexperia Home Platform PNX8550 System Chip," Proc. Design, Automation and Test in Europe Conf. (DATE 04), IEEE CS Press, 2004, pp. 108-113.
12. T. Waayers, R. Morren, and R. Grandi, "Definition of a Robust Modular SOC Test Architecture; Resurrection of the Single TAM Daisy-Chain," Proc. Int'l Test Conf. (ITC 05), IEEE CS Press, 2005, pp. 610-619.
13. Y. Zorian and S. Shoukourian, "Embedded Memory Test and Repair: Infrastructure IP for SoC Yield," IEEE Design &Test, vol. 20, no. 3, May-June 2003, pp. 58-66.
19 ms
(Ver 2.0)

Marketing Automation Platform Marketing Automation Tool