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Issue No.05 - September-October (2008 vol.25)
pp: 442-451
Matthias Kühnle , University of Karlsruhe
Michael Hübner , University of Karlsruhe
Jürgen Becker , University of Karlsruhe
Antonio Deledda , University of Bologna
Claudio Mucci , University of Bologna
Florian Ries , University of Bologna
Antonio Marcello Coppola , STMicroelectronics
Lorenzo Pieralisi , STMicroelectronics
Riccardo Locatelli , STMicroelectronics
Giuseppe Maruccia , STMicroelectronics
Tommaso DeMarco , STMicroelectronics
Fabio Campi , STMicroelectronics
ABSTRACT
This work focuses on the interconnect infrastructure, functionality, and capability of a heterogeneous reconfigurable SoC. This SoC integrates reconfigurable units of various granularity used as stream-processing elements. A network-on-chip (NoC) approach demonstrates benefits in scalability, flexibility, and runtime adaptivity for actual and future SoC designs. On a reference CMOS090 implementation, the described interconnect system works at the system frequency of 200 MHZ, sustaining the required runtime bandwidth for several application domains.
INDEX TERMS
heterogeneous processing, network on chip, reconfigurability, streaming, SoC
CITATION
Matthias Kühnle, Michael Hübner, Jürgen Becker, Antonio Deledda, Claudio Mucci, Florian Ries, Antonio Marcello Coppola, Lorenzo Pieralisi, Riccardo Locatelli, Giuseppe Maruccia, Tommaso DeMarco, Fabio Campi, "An Interconnect Strategy for a Heterogeneous, Reconfigurable SoC", IEEE Design & Test of Computers, vol.25, no. 5, pp. 442-451, September-October 2008, doi:10.1109/MDT.2008.150
REFERENCES
1. R. Hartenstein, "A Decade of Reconfigurable Computing: A Visionary Retrospective," Proc. Design, Automation and Test in Europe Conf. (DATE 01), IEEE CS Press, 2001, pp. 642-649.
2. M. Coppola et al., "Spidergon: A Novel On-Chip Communication Network," Proc. Int'l Symp. System-on-Chip (SoC 04), IEEE Press, 2004, pp. 15-16.
3. F. Thoma et al., "MORPHEUS: Heterogeneous Reconfigurable Computing," Proc. 17th Int'l Conf. Field Programmable Logic and Applications (FPL 07), IEEE Press, 2007, pp. 409-414.
4. M. Vorbach et al., "Reconfigurable Processor Architectures for Mobile Phones," Proc. Int'l Parallel and Distributed Processing Symp. (IPDPS 03), IEEE CS Press, 2003, pp. 6-11.
5. F. Campi et al., "A Dynamically Adaptive DSP for Heterogeneous Reconfigurable Platforms," Proc. Design, Automation and Test in Europe Conf. (DATE 07), IEEE CS Press, 2007, pp. 9-14.
6. S. Vassiliadis et al., "The MOLEN Polymorphic Processor," IEEE Trans. Computers, vol. 53, no. 11, Nov. 2004, pp. 1363-1375.
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