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An Interconnect Strategy for a Heterogeneous, Reconfigurable SoC
September-October 2008 (vol. 25 no. 5)
pp. 442-451
Matthias Kühnle, University of Karlsruhe
Michael Hübner, University of Karlsruhe
Jürgen Becker, University of Karlsruhe
Antonio Deledda, University of Bologna
Claudio Mucci, University of Bologna
Florian Ries, University of Bologna
Antonio Marcello Coppola, STMicroelectronics
Lorenzo Pieralisi, STMicroelectronics
Riccardo Locatelli, STMicroelectronics
Giuseppe Maruccia, STMicroelectronics
Tommaso DeMarco, STMicroelectronics
Fabio Campi, STMicroelectronics
This work focuses on the interconnect infrastructure, functionality, and capability of a heterogeneous reconfigurable SoC. This SoC integrates reconfigurable units of various granularity used as stream-processing elements. A network-on-chip (NoC) approach demonstrates benefits in scalability, flexibility, and runtime adaptivity for actual and future SoC designs. On a reference CMOS090 implementation, the described interconnect system works at the system frequency of 200 MHZ, sustaining the required runtime bandwidth for several application domains.

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Index Terms:
heterogeneous processing, network on chip, reconfigurability, streaming, SoC
Citation:
Matthias Kühnle, Michael Hübner, Jürgen Becker, Antonio Deledda, Claudio Mucci, Florian Ries, Antonio Marcello Coppola, Lorenzo Pieralisi, Riccardo Locatelli, Giuseppe Maruccia, Tommaso DeMarco, Fabio Campi, "An Interconnect Strategy for a Heterogeneous, Reconfigurable SoC," IEEE Design & Test of Computers, vol. 25, no. 5, pp. 442-451, Sept.-Oct. 2008, doi:10.1109/MDT.2008.150
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