The Changing Design Landscape
JULY-AUGUST 2008 (Vol. 25, No. 4) pp. 333
0740-7475/08/$31.00 © 2008 IEEE

Published by the IEEE Computer Society
The Changing Design Landscape
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Ajith Amerasekera, Texas Instruments
In 1965, Gordon Moore introduced his now famous law on the doubling of IC complexity. For many decades, this doubling has been realized through process technology innovation that has enabled semiconductors to achieve their complexity roadmap through scaling of transistor geometries. As we approach the 45-nm technology node of the International Technology Roadmap for Semiconductors ( ITRS), this scaling is alive and continuing, but some of the supporting infrastructure is not tracking it. In particular, performance is no longer increasing by significant amounts at every node. In conjunction with this, the equipment capabilities to print these incredibly small geometries are now the main driver for the process technology.
Moore's law still continues, and will do so as long as our system requirements expand at the existing rate. However, the burden of enabling Moore's law to continue is gradually moving from the process technologists to the designers-both circuit and system designers. Every two years or so, the increase in available capacity for integration exceeds the capability developed since Moore first proposed his law. For example, from 65 nm to 45 nm, the number of logic gates per square millimeter increased from 700,000 to 1.4 million. Considering that the Intel 486 processor, one of the technology drivers of the desktop computing era, had about 1 million transistors, this one process node provided an increase in capacity equivalent to an entire CPU, and at a far higher performance than was available back in the 1990s.
Table 1 shows what the scaling factors will be as we move from 65 nm to 22 nm. The number of transistors on a big chip will go from approximately 2 billion in 65 nm to 9 billion in 28 nm, to 15 billion in 22 nm. These are all huge numbers. The challenge is to build these chips with the same robustness, yield, and reliability as previous generations of chips.
The techniques described in "Reliable Systems on Unreliable Fabrics" (by Todd Austin et al.) in this issue of IEEE Design & Test describe some of the design issues related to this huge increase in complexity. In particular, technology scaling and the manufacturing process come with higher variations in transistors both locally and globally on a chip. Designers must account for this variation. Statistically, the large number of components on a single chip will lead to reliability, aging, and defect limitations that could no longer be eliminated through margins or overdesign. They must be detected and compensated without affecting the performance goals of the chip.
The research direction of the GSRC is aimed at solutions to these obstacles, for the continued advancement of system performance needs. Concepts such as error resiliency and fault-tolerant design are the first steps toward enabling chip designers to take control of their roadmap. Adaptive architectures and adaptive design will take advantage of the billions of transistors available in these nodes to provide techniques for ensuring robustness in these huge designs.
This is just the beginning of the work that must be done to build the large SoC designs with multibillion transistors that will be commonplace below the 32-nm technology node and beyond. GSRC researchers working with industry leaders will ensure that Moore's law continues to drive the electronics industry and the consumer world for many decades to come.
Ajith Amerasekera is a TI Fellow and ASIC CTO at Texas Instruments. Contact him at amerasekera@ti.com.

Table 1. Some typical transistor and gate metrics as technology scales from 65 nm to 22 nm.