Guest Editors' Introduction: System IC Design Challenges beyond 32 nm
JULY-AUGUST 2008 (Vol. 25, No. 4) pp. 294-295
0740-7475/08/$31.00 © 2008 IEEE

Published by the IEEE Computer Society
Guest Editors' Introduction: System IC Design Challenges beyond 32 nm
William H. Joyner, Semiconductor Research Corp.

David C. Yeh , Semiconductor Research Corp.
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Design of deeply scaled ICs is rapidly approaching the use of 32-nm lithography technology, and further scaling is already being planned. As the available number of raw transistors increases with each new technology node, the science of building electronic systems from the available devices is being strained to the point of breaking. Challenges such as increasing design complexity, fundamental power dissipation limits, the need for reliability in all operating modes, the continual demand for better overall system performance, and manufacturability concerns are leading to a reexamination of the current VLSI design methodology. The use of ICs as key components of electronic systems is changing the way design is done, because increasing system performance requires more attention at the system level and involves both hardware and software optimization. Leading academic researchers are addressing some of these challenges as part of the Gigascale Systems Research Center (GSRC). The charter of this multiuniversity research center is to establish a clear design process for the late-silicon age that can also serve as a bridge to emerging post-silicon technologies.
This special issue highlights ongoing research to address some of the challenges in the design of large ICs with dimensions well below 100 nm. The GSRC is organized around four themes and a design driver, and each is represented in this issue. There is also an exciting interview with Intel chair Craig Barrett.
In the first article, "Challenges and Solutions for Late- and Post-Silicon Design," Jan Rabaey and Sharad Malik (director and associate director of the GSRC) discuss where design is going as the technology roadmap evolves in multiple directions, variability and reliability increase as barriers, and system-level design comes of age. They describe the challenges at the top (with multicore architectures and concurrency) and at the bottom (with evolving new technologies in need of system design approaches), as well as the paths to address these challenges.
The interview in this issue is an interesting discussion with Craig Barrett. In addition to being the chair of Intel, Barrett is one of the fathers of the Focus Center Research Program (FCRP), and he chairs its governing council. In this wide-ranging interview, he discusses the industry challenges on the horizon, the role universities can play in addressing these challenges, the state and future of American education, and the value—and necessity—of collaborative programs.
Following this interview is "The Concurrency Challenge," by Wen-mei Hwu, Kurt Keutzer, and Timothy Mattson. Focusing on the hardware-software interface in multicore system design, the authors indicate how parallel computing—long a future solution to a wide range of problems (speed, power, complexity, and so on)—could finally be the path of choice to continue performance improvements. However, this success comes with a price: unprecedented advances in software technology will be required to keep pace with the advances in parallel-computing platforms.
Rather than assembling a working system from working parts, present and future designers will need to create systems that operate correctly from components that are inherently failure-prone. "Reliable Systems on Unreliable Fabrics," by Todd Austin et al., focuses on resilient systems that can operate successfully and recover from transient, manufacturing, infant mortality, and aging failures.
"The Search for Alternative Computational Paradigms," by Naresh Shanbhag et al., describes how variability, noise, soft errors, and other nonideal behaviors will require new computation models as the post-CMOS era approaches.
In the next article, Alberto Sangiovanni-Vincentelli asks, "Is a Unified Methodology for System-Level Design Possible?" He argues that a disciplined, platform-based design methodology is critical, not only to improve design productivity but also to ensure safe, secure, and effective design with heterogeneous components.
In the last article, "Workloads of the Future," Jan Rabaey et al. argue that new benchmarks, spanning a range of target applications, will be needed to guide the exploration and optimization of future systems.
Accompanying the theme articles are three sidebars written by industry leaders (Richard Oehler of AMD, Ajith Amerasekera of Texas Instruments, and Leon Stok of IBM) on the challenges they see on the horizon, the paths being taken to address these challenges, and the role university programs can play. In addition, a Perspectives article by John Zolper discusses the value of this collaborative program to US national interests, including national security.
Finally, in the Last Byte, FCRP executive director Betsy Weitzman looks back at the genesis of the FCRP, and looks forward to more groundbreaking research through multiuniversity collaboration and an industry-government-academia partnership.
We hope you find &SetFont Typeface="44";this special issue interesting and thought-provoking. The research described here highlights the collaborative nature of the GSRC and the FCRP, as the industry continues to drive forward to provide increased capability for electronic system design.

William H. Joyner Jr. is on assignment from IBM as director of Computer-Aided Design and Test at Semiconductor Research Corp. His research interests include software and hardware verification, logic synthesis and simulation, and physical design. He has a BS in engineering science from the University of Virginia and a PhD in applied mathematics from Harvard University. He is a Fellow of the IEEE.

David C. Yeh is on assignment from Texas Instruments as director of Integrated Circuits and Systems Sciences at Semiconductor Research Corp. His research interests include high-speed, low-power, robustness, and manufacturability issues for digital, analog, mixed-signal, and RF IC designs. He has a BS, an MS, and a PhD in electrical engineering, all from the University of Illinois at Urbana-Champaign. He is a senior member of the IEEE.