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Issue No.04 - July-August (2008 vol.25)
pp: 294-295
William H. Joyner Jr. , Semiconductor Research Corp.
David C. Yeh , Semiconductor Research Corp.
ABSTRACT
This special issue highlights ongoing research to address some of the challenges in the design of large ICs with dimensions well below 100 nm. The Gigascale Systems Research Center is organized around four themes and a design driver, and each is represented in this issue. There is also an exciting interview with Intel chair Craig Barrett. Accompanying the theme articles are three sidebars written by industry leaders (Richard Oehler of AMD, Ajith Amerasekera of Texas Instruments, and Leon Stok of IBM) on the challenges they see on the horizon, the paths being taken to address these challenges, and the role university programs can play. In addition, a Perspectives article by John Zolper discusses the value of this collaborative program to US national interests, including national security. Finally, there is a Last Byte column by the FCRP executive director Betsy Weitzman.
INDEX TERMS
Gigascale Systems Research Center, multiuniversity research center, large ICs, 32 nm, Craig Barrett, Focus Center Research Program
CITATION
William H. Joyner Jr., David C. Yeh, "Guest Editors' Introduction: System IC Design Challenges beyond 32 nm", IEEE Design & Test of Computers, vol.25, no. 4, pp. 294-295, July-August 2008, doi:10.1109/MDT.2008.95
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