Issue No.03 - May-June (2008 vol.25)
Rudolf Schlangen , Berlin University of Technology
Christian Boit , Berlin University of Technology
Ted Lundquist , DCG Systems
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2008.82
The prerequisite to physical analysis for IC functionality in nanoscale technologies is access through the chip backside. Based on typical global backside preparation with a moderate silicon thickness of 50 to 100 microns remaining, the authors of this article survey the analysis techniques available for this purpose and evaluate them for functional analysis and resolution potential. They also present a circuit edit (CE) technique that is valid for nanotechnology ICs. This technique is based on the formation of local trenches using the bottom of shallow trench isolation (STI) as the endpoint for focused ion beam (FIB) milling. As a derivative of this process, an ultrathin silicon device can be processed, enabling the breakthrough application of nanoscale analysis techniques to a fully functional circuit through the chip backside. Several applications demonstrate how powerful this approach can be.
debug, nanoscale, optical probing, backside, time-resolved emission, laser voltage probing, electron beam probing, thermal laser stimulation, photoelectric laser stimulation
Rudolf Schlangen, Christian Boit, Ted Lundquist, "Physical Techniques for Chip-Backside IC Debug in Nanotechnologies", IEEE Design & Test of Computers, vol.25, no. 3, pp. 250-257, May-June 2008, doi:10.1109/MDT.2008.82