The Community for Technology Leaders
RSS Icon
Subscribe
Issue No.03 - May-June (2008 vol.25)
pp: 224-230
Kip Killpack , Intel
Pouria Bastani , University of California, Santa Barbara
ABSTRACT
Fast time to market and high performance translate to improved profit margins in the microprocessor business. The microprocessor design flow first involves design and timing convergence, then several iterations of frequency pushes on silicon, and finally volume production and sale to the market. Inevitably, speed failures occur because of frequency pushes, and these are prioritized on the basis of severity. Practical aspects such as time-to-market requirements limit the magnitude of eventual frequency push based on the amount of failures that can be analyzed. The authors of this article have analyzed 56 speed failures to understand the underlying causes. Specifically, they have studied the effects of multiple-input switching, cross-coupling noise, and localized voltage droop. Understanding the causes of speed failures provides insight so that designers can develop design strategies for better power-performance tradeoffs.
INDEX TERMS
cross-coupling noise, multiple-input switching, voltage droop, silicon debug, critical path, microprocessor, diagnosis, marginality
CITATION
Kip Killpack, Suriyaprakash Natarajan, Arun Krishnamachary, Pouria Bastani, "Case Study on Speed Failure Causes in a Microprocessor", IEEE Design & Test of Computers, vol.25, no. 3, pp. 224-230, May-June 2008, doi:10.1109/MDT.2008.61
REFERENCES
1. B. Gottlieb et al., "Silicon Debug: What Do You Do When Your ASIC Does Not Work as Fast as Expected?," presented at 41st Design Automation Conf., 2004.
2. K. Killpack, C. Kashyap, and E. Chiprout, "Silicon Speed Path Measurement and Feedback into EDA Flows," Proc. 44th Design Automation Conf., ACM Press, 2007, pp. 390-395.
3. K. Killpack, "A Fast Tolerance-Based Incremental Timing Analysis Algorithm," Proc. ACM/IEEE Int'l Workshop Timing Issues in the Specification and Synthesis of Digital Systems, 2007, pp. 137-142.
4. A. Agarwal, D. Blaauw, and F. Dartu, "Statistical Gate Delay Model Considering Multiple Input Switching," Proc. 41st Design Automation Conf., ACM Press, 2004, pp. 658-663.
5. J. Sridharan and T. Chen, "Gate Delay Modeling with Multiple Input Switching for Static (Statistical) Timing Analysis," Proc. Int'l Conf. VLSI Design, IEEE CS Press, 2006, pp. 323-328.
6. A. Kahng, S. Muddu, and E. Sarto, "On Switch Factor Based Analysis of Coupled RC Interconnects," Proc. 37th Design Automation Conf., ACM Press, 2000, pp. 79-84.
7. I. Keller, K. Tseng, and N.K. Verghese, "A Robust Cell-Level Crosstalk Delay Change Analysis," Proc. Int'l Conf. Computer-Aided Design (ICCAD), IEEE CS Press, 2004, pp. 147-154.
8. S. Pant and E. Chiprout, "Power Grid Physics and Implications for CAD," Proc. 43rd Design Automation Conf., ACM Press, 2006, pp. 199-204.
6 ms
(Ver 2.0)

Marketing Automation Platform Marketing Automation Tool