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Issue No.03 - May-June (2008 vol.25)
pp: 216-223
ABSTRACT
First-silicon validation and debug require a labor-intensive engineering effort of several months and have become the least predictable and most time-consuming part of a new 90-nm chip's development cycle. Lack of adequate tools and automatic procedures is a big factor in this bottleneck. Other difficulties include nondeterministic operation and lack of time-specific expected values. This article presents a new approach that provides an efficient scalable solution to overcome these difficulties. The end results are a significant reduction of the silicon validation and debug time, and faster discovery and root-cause determination of integration problems, design bugs, and chip defects.
INDEX TERMS
silicon validation, silicon debug, logic analysis, on-chip instrumentation, assertions, reconfigurable infrastructure, system validation
CITATION
Miron Abramovici, "In-System Silicon Validation and Debug", IEEE Design & Test of Computers, vol.25, no. 3, pp. 216-223, May-June 2008, doi:10.1109/MDT.2008.77
REFERENCES
1. B. Vermeulen and S.K. Goel, "Design for Debug: Catching Design Errors in Digital Chips," IEEE Design &Test, vol. 19, no. 3, May/June 2002, pp. 35-43.
2. M. Abramovici et al., "A Reconfigurable Design-for-Debug Infrastructure for SoCs," Proc. 43rd Design Automation Conf. (DAC 06), ACM Press, 2006, pp. 7-12.
3. DAFCA, http:/www.dafca.com.
4. B. Vermeulen, T. Waayers, and S.K. Goel, "Core-Based Scan Architecture for Silicon Debug," Proc. Int'l Test Conf. (ITC 02), IEEE CS Press, 2002, pp. 638-647.
5. P. Dahlgren, P. Dickinson, and I. Parulkar, "Latch Divergency in Microprocessor Failure Analysis," Proc. Int'l Test Conf. (ITC 03), IEEE CS Press, 2003, pp. 755-763.
6. V.K. Reddy, A.S. Al-Zawawi, and E. Rotenberg, "Assertion-Based Microarchitecture Design for Improved Fault Tolerance," Proc. 24th Int'l Conf. Computer Design (ICCD 06), IEEE CS Press, 2006.
7. M. Boule, J.-S Chenard, and Z. Zilic, "Assertion Checkers in Verification, Silicon Debug and In-Field Diagnosis," Proc. 8th Int'l Symp. Quality Electronic Design (ISQED 07), IEEE CS Press, 2007, pp. 613-620.
8. M. Abramovici, Method to Locate Logic Errors and Defects in Digital Circuits, US patent 7,296,201, to DAFCA, Patent and Trademark Office, 2007.
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