The Community for Technology Leaders
RSS Icon
Subscribe
Issue No.03 - May-June (2008 vol.25)
pp: 208-215
Bart Vermeulen , NXP Semiconductors
ABSTRACT
Design for debug is the act of adding debug support to a chip's design in the realization that not every silicon chip or embedded-software application is right the first time. DFD gives debug engineers increased observability of an embedded system's internal operation. There are severe constraints, however, on the amount of debug observability that DFD can provide for error localization. In practice, to bridge the gap between the amount of on-chip data and the limited off-chip bandwidth, SoC designers use two complementary approaches to transport valuable internal debug information: run-stop debug and real-time trace debug. This article presents an overview of these techniques and describes the required hardware support. The article also shows how these techniques have been successfully applied to debug the prototype silicon and embedded software of industrial SoCs.
INDEX TERMS
silicon debug, silicon validation, functional debugging, debug use cases
CITATION
Bart Vermeulen, "Functional Debug Techniques for Embedded Systems", IEEE Design & Test of Computers, vol.25, no. 3, pp. 208-215, May-June 2008, doi:10.1109/MDT.2008.66
REFERENCES
1. A. Hopkins and K. McDonald-Maier, "Debug Support for Complex Systems On-Chip: A Review," IEE Proc. Computers and Digital Techniques, vol. 153, no. 4, July 2006, pp. 197-207.
2. S.K. Goel and B. Vermeulen, "Data Invalidation Analysis for Scan-Based Debug on Multiple-Clock System Chips," J. Electronic Testing: Theory and Applications, vol. 19, no. 4, Aug. 2003, pp. 407-416.
3. P. Dahlgren, P. Dickinson, and I. Parulkar, "Latch Divergency in Microprocessor Failure Analysis," Proc. Int'l Test Conf. (ITC 03), IEEE CS Press, 2003, pp. 755-763.
4. K. Goossens et al., "Transaction-Based Communication-Centric Debug," Proc. 1st Int'l Symp. Networks-on-Chip (NOCs 07), IEEE Press, 2007, pp. 95-106.
5. R. Leatherman and N. Stollon, "An Embedded Debugging Architecture for SoCs," IEEE Potentials, vol. 24, no. 1, Feb.-Mar. 2005, pp. 12-16.
6. "CoreSight Technology System Design Guide," ARM, http://infocenter.arm.com/help/index.jsp?topic = com.arm.doc.dgi0012b.
7. K. Holdbrook et al., "MicroSPARC: A Case Study of Scan-Based Debug," Proc. Int'l Test Conf. (ITC 94), IEEE CS Press, 1994, pp. 70-75.
8. M. Abramovici et al., "A Reconfigurable Design-for-Debug Infrastructure for SoCs," Proc. 43rd Design Automation Conf. (DAC 06), ACM Press, 2006, pp. 7-12.
9. B. Vermeulen, S. Oostdijk, and F. Bouwman, "Test and Debug Strategy of the PNX8525 Nexperia Digital Video Platform System Chip," Proc. Int'l Test Conf. (ITC 01), IEEE CS Press, 2001, pp. 121-130.
10. A. Abbo et al., "Xetal-II: A 107 GOPS, 600 mW Massively Parallel Processor for Video Scene Analysis," IEEE J. Solid-State Circuits, vol. 43, no. 1, Jan. 2008, pp. 192-201.
11. B. Vermeulen and S. Bakker, "Debug Architecture for the En-II System Chip," Computers and Digital Techniques, vol. 1, no. 6, Nov. 2007, pp. 678-684.
12. M. Boule, J.-S Chenard, and Z. Zilic, "Debug Enhancements in Assertion-Checker Generation," Computers and Digital Techniques, vol. 1, no. 6, Nov. 2007, pp. 669-677.
11 ms
(Ver 2.0)

Marketing Automation Platform Marketing Automation Tool