Issue No.02 - March-April (2008 vol.25)
Ganesh Srinivasan , Texas Instruments
Friedrich Taenzler , Texas Instruments
Abhijit Chatterjee , Georgia Institute of Technology
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2008.46
Recent advances in design and process technologies of wireless transceivers have enabled RF IC manufactures to reduce die costs thorough higher levels of integration. This often causes an opposite reaction from the packaging and test costs because of the increase in device complexity. One way to eliminate unnecessary packaging costs and lower final test costs is to introduce simple, low-cost, and well-structured wafer sort tests for RF paths in addition to well-established DC probe tests. This article presents a loopback DFT approach to overcome limitations of conventional loopback approaches for wafer probe tests of single-VCO-based transceiver architectures. Go/no-go tests derived using the loopback DFT are used to screen dies during wafer probe. A study of the test yield observed during final test with and without the proposed loopback DFT tests performed on Texas Instruments TRF6903 devices is presented to validate the approach.
RF test, DFT, low-cost test, wafer probe test, test yield, loopback test
Ganesh Srinivasan, Friedrich Taenzler, Abhijit Chatterjee, "Loopback DFT for Low-Cost Test of Single-VCO-Based Wireless Transceivers", IEEE Design & Test of Computers, vol.25, no. 2, pp. 150-159, March-April 2008, doi:10.1109/MDT.2008.46