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Hierarchical Test Compression for SoC Designs
March-April 2008 (vol. 25 no. 2)
pp. 142-148
Kee Sup Kim, Intel
Ming Zhang, Intel
For SOC designs, it becomes very desirable to have IP blocks that come with their own test compression while having a second level of compression at the full-chip level. If done without careful analysis, this second-level compression logic can be subject to much greater aliasing and error masking because of the presence of X (unknown) values. This article presents a systematic way of designing the second-level compression logic. This method preserves the same X and multiple-error tolerance as the original X-Compact. The new method also successfully handles the use of identical cores, where there is a far higher chance of multiple errors and X values.

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Index Terms:
hierarchical, test compression, SoC
Kee Sup Kim, Ming Zhang, "Hierarchical Test Compression for SoC Designs," IEEE Design & Test of Computers, vol. 25, no. 2, pp. 142-148, March-April 2008, doi:10.1109/MDT.2008.39
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