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Issue No.02 - March-April (2008 vol.25)
pp: 132-140
Chao-Wen Tzeng , National Tsing-Hua University
Shi-Yu Huang , National Tsing-Hua University
This article presents a universal-multicasting scan architecture for test compression. By universal multicasting, the authors mean that a specific test pattern can be multicast to a set of any desired scan chains as long as they are compatible. It does require the addition of some extra control bits padded to the compressed test patterns. However, by incorporating techniques such as control pattern encoding, skipping, and partial data reuse, the authors demonstrate that the control overhead can be reduced to a modest level. This method improves the test compression ratio substantially over the recent software-defined multicasting methodology, most notably the segmented addressable scan (SAS). Experimental results indicate that up to 51x test compression ratio in both test data volume and test time can be achieved for a real design with a 1.3% care bit ratio in the test set.
test compression, DFT, scan test, broadcasting, multicasting
Chao-Wen Tzeng, Shi-Yu Huang, "UMC-Scan Test Methodology: Exploiting the Maximum Freedom of Multicasting", IEEE Design & Test of Computers, vol.25, no. 2, pp. 132-140, March-April 2008, doi:10.1109/MDT.2008.55
1. K.-J Lee, J.J. Chen, and C.H. Huang, "Using a Single Input to Support Multiple Scan Chains," Proc. Int'l Conf. Computer-Aided Design (ICCAD 98), IEEE CS Press, 1998, pp. 74-78.
2. I. Jamzaoglu and J.H. Patel, "Reducing Test Application Time for Full Scan Embedded Cores," Proc. 29th Ann. Int'l Symp. Fault-Tolerant Computing (FTCS 99), IEEE CS Press, 1999, pp. 260-267.
3. P.-C Tsai and S.-J Wang, "Multi-mode Segmented Scan Architecture with Layout-Aware Scan Chain Routing for Test Data and Test Time Reduction," Proc. 15th Asian Test Symp. (ATS 06), IEEE CS Press, 2006, pp. 225-230.
4. A. Al-Yamani, E. Chmelar, and M. Grinchuck, "Segmented Addressable Scan Architecture," Proc. 23rd IEEE VLSI Test Symp. (VTS 05), IEEE CS Press, 2005, pp. 405-411.
5. L.-T Wang, C.-W Wu, and X. Wen, Design for Testability: VLSI Test Principles and Architectures, Morgan Kaufmann, 2006.
6. A. Jas et al., "An Efficient Test Vector Compression Scheme Using Selective Huffman Coding," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 6, June 2003, pp. 797-806.
7. M.H. Tehranipour, M. Nourani, and K. Chakrabarty, "Nine-Coded Compression Technique with Application to Reduced Pin-Count Testing and Flexible On-Chip Decompression," Proc. Design, Automation and Test in Europe Conf. (DATE 04), IEEE CS Press, vol. 2, 2004, pp. 1284-1289.
8. M. Nourani and M. Tehranipour, "RL-Huffman Encoding for Test Compression and Power Reduction in Scan Applications," ACM Trans. Design Automation of Electronic Systems, vol. 10, no. 1, Jan. 2005, pp. 91-115.
9. J. Rajski et al., "Embedded Deterministic Test," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 23, no. 5, May 2004, pp. 776-792.
10. N. Sitchinava et al., "Changing the Scan Enable During Shift," Proc. 22nd IEEE VLSI Test Symp. (VTS 04), IEEE CS Press, 2004, pp. 73-78.
11. L.-T Wang et al., "VirtualScan: A New Compressed Scan Technology for Test Cost Reduction," Proc. Int'l Test Conf. (ITC 04), IEEE CS Press, 2004, pp. 916-925.
12. S.-P Lin et al., "A Multiplayer Data Copy Test Data Compression Scheme for Reducing Shifting-In Power for Multiple Scan Design," IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 15, no. 7, July 2007, pp. 767-776.
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