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Issue No.02 - March-April (2008 vol.25)
pp: 122-130
Laung-Terng Wang , SynTest Technologies
Xiaoqing Wen , Kyushu Institute of Technology
Shianling Wu , SynTest Technologies
Zhigang Wang , Cisco Systems
Zhigang Jiang , SynTest Technologies
Boryau Sheu , SynTest Technologies
Xinli Gu , Cisco Systems
ABSTRACT
This article describes a test compression technology, called VirtualScan, which achieves scan test cost reduction by inserting a small combinational broadcaster and compactor into the original circuit under test (CUT). In addition, one-pass ATPG takes into account all constraints imposed by the VirtualScan compression architecture, and generates compression test patterns in the same manner as a conventional full-scan ATPG. The simplicity of the combinational-logic-based compression technology further allows for flexibility in addressing unknown (X) values and fault-aliasing effects, through either an enhanced ATPG algorithm or enhanced compactor logic.
INDEX TERMS
ATPG, scan testing, test compression, combinational broadcaster, combinational compactor, low-power testing, fault diagnosis
CITATION
Laung-Terng Wang, Xiaoqing Wen, Shianling Wu, Zhigang Wang, Zhigang Jiang, Boryau Sheu, Xinli Gu, "VirtualScan: Test Compression Technology Using Combinational Logic and One-Pass ATPG", IEEE Design & Test of Computers, vol.25, no. 2, pp. 122-130, March-April 2008, doi:10.1109/MDT.2008.56
REFERENCES
1. L.-T Wang, C.-W Wu, and X. Wen eds. , VLSI Test Principles and Architectures: Design for Testability, Morgan Kaufmann, 2006.
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7. L.-T Wang et al., "VirtualScan: A New Compressed Scan Technology for Test Cost Reduction," Proc. Int'l Test Conf. (ITC 04), IEEE CS Press, 2004, pp. 916-925.
8. Z. Wang et al., Compacting Test Responses Using X-Driven Compactor, US patent application 11/898,070, SynTest Technologies.
9. N.A. Touba, "X-Canceling MISR: An X-Tolerant Methodology for Compacting Output Responses with Unknowns Using a MISR," Proc. Int'l Test Conf. (ITC 07), IEEE CS Press, no. 4437576, 2007, p. 10.
10. S. Mitra and K. Kim, "X-Compact: An Efficient Response Compaction Technique," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Mar. 2004, pp. 421-432.
11. W.-T Cheng et al., "Diagnose Compound Scan Chain and System Logic Defects," Proc. Int'l Test Conf. (ITC 07), IEEE CS Press, no. 4437578, 2007, p. 10.
12. P. Girard, X. Wen, and N.A. Touba, "Low-Power Testing," System-on-Chip Test Architectures: Nanometer Design for Testability, L.-T Wang, C.E. Stroud, and N.A. Touba eds. Morgan Kaufmann, 2007, pp. 307-350.
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