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Historical Perspective on Scan Compression
March-April 2008 (vol. 25 no. 2)
pp. 114-120
Rohit Kapur, Synopsys
Subhasish Mitra, Stanford University
Since gaining popularity in the late 1990s, the term "scan compression" has maintained a solid hold within the IC test lexicon. In recent years, however, this technology has taken the test industry by storm. As the cost of test increased to previously unseen heights, some companies complained that the cost to test a single transistor was nearly equal to the cost of manufacturing it. Scan compression technology, however, proved to be a powerful antidote to this problem, as it catalyzed reductions in test data volume and test application time of up to 100x. As a result, the cost of test may well be contained for many years to come. This article sketches a brief history of test technology research that has led to the stunning success of scan compression. This article is not intended to attribute inventors for innovations on a fine-grained timeline. The important concepts of technologies are presented at the high level on a coarse timeline.

1. N.A. Touba, "Survey of Test Vector Compression Techniques," IEEE Design &Test, vol. 23, no. 4, July-Aug. 2006, pp. 294-303.
2. M.J. Guezebroek et al., "Test Point Insertion for Compact Test Sets," Proc. Int'l Test Conf. (ITC 00), IEEE CS Press, 2000, pp. 292-301.
3. P.H. Bardell and W.H. McAnney, "Self-Testing of Multichip Logic Modules," Proc. Int'l Test Conf. (ITC 82), IEEE CS Press, 1982, pp. 200-204.
4. B. Koenemann, "LFSR-Coded Test Patterns for Scan Designs," Proc. European Test Conf., IEEE CS Press, 1991, pp. 581-590.
5. I. Hamzaoglu and J. Patel, "Reducing Test Application Time for Full Scan Embedded Cores," Proc. 29th Ann. Symp. Fault Tolerant Computing (FTCS 99), IEEE CS Press, 1999, pp. 260-267.
6. C. Barnhart et al., "OPMISR: The Foundation for Compressed ATPG Vectors," Proc. Int'l Test Conf. (ITC 01), IEEE CS Press, 2001, pp. 748-757.
7. S. Mitra and K.S. Kim, "XPAND: An Efficient Test Stimulus Compression Technique," IEEE Trans. Computers, vol. 55, no. 2, Feb. 2006, pp. 163-173.
8. L.-T Wang et al., "VirtualScan: A New Compressed Scan Technology for Test Cost Reduction," Proc. Int'l Test Conf. (ITC), IEEE CS Press, 2004, pp. 916-925.
9. N. Sitchinava et al., "Changing the Scan Enable During Shift," Proc. VLSI Test Symp. (VTS 04), IEEE CS Press, 2004, pp. 73-78.
10. J. Rajski et al., "Embedded Deterministic Test," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 23, no. 5, May 2004, pp. 776-792.
11. S. Mitra and K.S. Kim, "X-Compact: An Efficient Response Compaction Technique for Test Cost Reduction," Proc. Int'l Test Conf. (ITC 02), IEEE CS Press, 2002, pp. 311-320.
12. J. Rajski et al., "Convolutional Compaction of Test Responses," Proc. Int'l Test Conf. (ITC 03), IEEE CS Press, 2003, pp. 745-754.
13. Z. Stanojevic et al., "Enabling Yield Analysis with X-Compact," Proc. Int'l Test Conf. (ITC 05), IEEE CS Press, 2005, pp. 726-734.
14. A. Leininger et al., "Compression Mode Diagnosis Enables High Volume Monitoring Diagnosis Flow," Proc. Int'l Test Conf. (ITC 05), IEEE CS Press, 2005, pp. 156-165.
15. P. Wohl et al., "Minimizing the Impact of Scan Compression," Proc. VLSI Test Symp. (VTS 07), IEEE CS Press, 2007, pp. 67-74.

Index Terms:
IC testing, scan compression, test data volume reduction, test application time reduction
Citation:
Rohit Kapur, Subhasish Mitra, Thomas W. Williams, "Historical Perspective on Scan Compression," IEEE Design & Test of Computers, vol. 25, no. 2, pp. 114-120, March-April 2008, doi:10.1109/MDT.2008.40
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