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March-April 2008 (vol. 25 no. 2)
pp. 105
Test data compression became an active research topic in the late 1990s, and has now become a standard offering within commercial DFT solutions. This issue of IEEE Design & Test features a special issue on the current state of test compression. This issue of D&T also concludes the theme of design and test of RFIC chips (featured in the Jan./Feb. 08 issue), with two additional articles. In addition, this issue features two general-interest articles and an interview with DRAM inventor Bob Dennard.
Index Terms:
test compression, test vectors, DFT, RFIC chips, Bob Dennard
Citation:
Tim Cheng, "Test compression saves bits, cycles, and money," IEEE Design & Test of Computers, vol. 25, no. 2, pp. 105, March-April 2008, doi:10.1109/MDT.2008.52
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