CSDL - IEEE Design and Test of Computers

Design&Test
2008
Issue No. 2 - March-April

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IEEE Design & Test of Computers

March-April 2008 (vol. 25 no. 2)

ISSN: 0740-7475

Table of Contents

From the EIC

Test compression saves bits, cycles, and money (HTML)

pp. 105

Special Issue Features

Guest Editors' Introduction: Progress in Test Compression (HTML)

Scott Davidson, Sun Microsystems

Nur A. Touba, University of Texas at Austin

pp. 112-113

ABSTRACT

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Historical Perspective on Scan Compression (Abstract)

Rohit Kapur, Synopsys

Subhasish Mitra, Stanford University

Thomas W. Williams, Synopsys

pp. 114-120

ABSTRACT

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VirtualScan: Test Compression Technology Using Combinational Logic and One-Pass ATPG (Abstract)

Laung-Terng Wang, SynTest Technologies

Xiaoqing Wen, Kyushu Institute of Technology

Shianling Wu, SynTest Technologies

Zhigang Wang, Cisco Systems

Zhigang Jiang, SynTest Technologies

Boryau Sheu, SynTest Technologies

Xinli Gu, Cisco Systems

pp. 122-130

ABSTRACT

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UMC-Scan Test Methodology: Exploiting the Maximum Freedom of Multicasting (Abstract)

Chao-Wen Tzeng, National Tsing-Hua University

Shi-Yu Huang, National Tsing-Hua University

pp. 132-140

ABSTRACT

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Hierarchical Test Compression for SoC Designs (Abstract)

Kee Sup Kim, Intel

Ming Zhang, Intel

pp. 142-148

ABSTRACT

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RFIC Chips, Part 2

Loopback DFT for Low-Cost Test of Single-VCO-Based Wireless Transceivers (Abstract)

Ganesh Srinivasan, Texas Instruments

Friedrich Taenzler, Texas Instruments

Abhijit Chatterjee, Georgia Institute of Technology

pp. 150-159

ABSTRACT

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Wireless System for Microwave Test Signal Generation (Abstract)

Qizhang Yin, Monolithic Power Systems

William R. Eisenstadt, University of Florida

Tian Xia, Spansion

pp. 160-166

ABSTRACT

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Other Features

An Illustrated Methodology for Analysis of Error Tolerance (Abstract)

Melvin A. Breuer, University of Southern California

Haiyang (Henry) Zhu, Analog Devices

pp. 168-177

ABSTRACT

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Device Model for Ballistic CNFETs Using the First Conducting Band (Abstract)

Hamidreza Hashempour, NXP Semiconductors

Fabrizio Lombardi, Northeastern University

pp. 178-186

ABSTRACT

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DATC Newsletter

DATC Newsletter (HTML)

pp. 187

Interview

Discussing DRAM and CMOS Scaling with Inventor Bob Dennard (Abstract)

pp. 188-191

ABSTRACT

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Standards

Standards update from IP 07 (Abstract)

Victor Berman, Improv Systems

pp. 192-193

ABSTRACT

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Book Reviews

Building your yield of dreams (HTML)

Sachin Sapatnekar, University of Minnesota

pp. 194-195

ABSTRACT

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CEDA Currents

CEDA Currents (HTML)

pp. 196-197

ABSTRACT

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TTTC Newsletter

TTTC Newsletter (HTML)

pp. 198-199

The Last Byte

The commonality of vector generation techniques (Abstract)

Scott Davidson, Sun Microsystems

pp. 200

ABSTRACT

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