Issue No.01 - January-February (2008 vol.25)
Daniele Rossi , University of Bologna
André K. Nieuwland , NXP Semiconductors
Cecilia Metra , University of Bologna
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2008.25
As device geometries shrink and power supply voltages decrease, simultaneous switching noise (SSN) is having a detrimental effect on IC reliability. This article analyzes the impact of different bus transitions on SSN. Transitions involving the same number of switching signals, but with different placement of switching wires (different switching patterns) within the bus, can induce considerably different levels of SSN. The authors evaluate how SSN varies as a function of the number of switching wires, for different values of wire capacitances. They find that a piecewise linear dependency exists between the SSN and the number of switching wires when the coupling capacitance between adjacent wires is taken into account. Additionally, they analyze the impact of the switching patterns on the effectiveness of the coding techniques that are often proposed to reduce the amount of switching wires and hence SSN. They show that switching-pattern and layout considerations have a significant impact on coding performance. The authors perform their analysis considering realistic bus and power supply network models, both implemented using standard 0.13-micron CMOS technology.
simultaneous switching noise, bus layout, coding techniques, IC, system reliability, switching patterns, power supply network
Daniele Rossi, André K. Nieuwland, Cecilia Metra, "Simultaneous Switching Noise: The Relation between Bus Layout and Coding", IEEE Design & Test of Computers, vol.25, no. 1, pp. 76-86, January-February 2008, doi:10.1109/MDT.2008.25