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Hybrid-SBST Methodology for Efficient Testing of Processor Cores
January-February 2008 (vol. 25 no. 1)
pp. 64-75
Nektarios Kranitis, University of Athens
Andreas Merentitis, University of Athens
George Theodorou, University of Athens
Antonis Paschalis, University of Athens
Dimitris Gizopoulos, University of Piraeus
Software-based self-test (SBST) has recently emerged as an effective methodology for the manufacturing test of embedded processors in SoCs. SBST is a nonintrusive approach that has the potential to provide high-quality at-speed testing at virtually zero performance, power, and circuit area overhead, using low-speed, low-cost external ATE. However, modern commercial processor cores are characterized by a high level of complexity, and their architectural features introduce test challenges that no single test methodology can effectively address. In this article, the authors combine self-test programs based on deterministic SBST methodologies (using high-level test development and gate-level-constrained ATPG test development) with verification-based self-test programs and directed random test program generation (RTPG), to develop a very effective hybrid-SBST test strategy. The authors applied this H-SBST strategy to the OpenRISC 1200 embedded processor. Experimental results show test coverage of more than 92%, demonstrating the effectiveness of the proposed methodology.

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Index Terms:
microprocessor testing, functional testing, software-based self-test, H-SBST, computer architecture, ATPG, RTPG
Citation:
Nektarios Kranitis, Andreas Merentitis, George Theodorou, Antonis Paschalis, Dimitris Gizopoulos, "Hybrid-SBST Methodology for Efficient Testing of Processor Cores," IEEE Design & Test of Computers, vol. 25, no. 1, pp. 64-75, Jan.-Feb. 2008, doi:10.1109/MDT.2008.15
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