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Issue No.01 - January-February (2008 vol.25)
pp: 64-75
Nektarios Kranitis , University of Athens
Andreas Merentitis , University of Athens
George Theodorou , University of Athens
Antonis Paschalis , University of Athens
Dimitris Gizopoulos , University of Piraeus
ABSTRACT
Software-based self-test (SBST) has recently emerged as an effective methodology for the manufacturing test of embedded processors in SoCs. SBST is a nonintrusive approach that has the potential to provide high-quality at-speed testing at virtually zero performance, power, and circuit area overhead, using low-speed, low-cost external ATE. However, modern commercial processor cores are characterized by a high level of complexity, and their architectural features introduce test challenges that no single test methodology can effectively address. In this article, the authors combine self-test programs based on deterministic SBST methodologies (using high-level test development and gate-level-constrained ATPG test development) with verification-based self-test programs and directed random test program generation (RTPG), to develop a very effective hybrid-SBST test strategy. The authors applied this H-SBST strategy to the OpenRISC 1200 embedded processor. Experimental results show test coverage of more than 92%, demonstrating the effectiveness of the proposed methodology.
INDEX TERMS
microprocessor testing, functional testing, software-based self-test, H-SBST, computer architecture, ATPG, RTPG
CITATION
Nektarios Kranitis, Andreas Merentitis, George Theodorou, Antonis Paschalis, Dimitris Gizopoulos, "Hybrid-SBST Methodology for Efficient Testing of Processor Cores", IEEE Design & Test of Computers, vol.25, no. 1, pp. 64-75, January-February 2008, doi:10.1109/MDT.2008.15
REFERENCES
1. N. Kranitis et al., "Software-Based Self-Testing of Embedded Processors," IEEE Trans. Computers, vol. 54, no. 4, Apr. 2005, pp. 461—475.
2. A. Paschalis and D. Gizopoulos, "Effective Software-Based Self-Test Strategies for On-Line Periodic Testing of Embedded Processors," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 24, no. 1, Jan. 2005, pp. 88—99.
3. N. Kranitis et al., "Instruction-Based Self-Testing of Processor Cores," Proc. 20th IEEE VLSI Test Symp. (VTS 02), IEEE CS Press, 2002, pp. 223—228.
4. L. Chen et al., "A Scalable Software-Based Self-Test Methodology for Programmable Processors," Proc. 40th Design Automation Conf. (DAC 03), ACM Press, 2003, pp. 548—553.
5. C.H.P. Wen et al., "Simulation-Based Target Test Generation Techniques for Improving the Robustness of a Software-Based-Self-Test Methodology," Proc. IEEE Int'l Test Conf. (ITC 05), IEEE CS Press, 2005, pp. 936—945.
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