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Issue No.01 - January-February (2008 vol.25)
pp: 44-51
John Mark Nolen , Texas A&M University
Rabi N. Mahapatra , Texas A&M University
ABSTRACT
Much current research has focused on employing networks on chips (NoCs) for communication among numerous cores on large-scale SoCs. One side benefit of such designs is the potential to use this communication infrastructure with little modification for manufacturing test delivery. This article presents a test-scheduling approach for such designs that minimizes test time through high-speed test delivery over the network and lower-rate test execution at the target cores. To achieve this, the authors interleave test data over the network via time-division multiplexing (TDM). To demonstrate the utility of this approach, they present a test-scheduling algorithm and a simulated test case from ITC 2002 SoC benchmarks. The results show significant test time and I/O savings when compared to a single-clock approach.
INDEX TERMS
embedded-core testing, SoC, NoC, test access mechanism, TAM, scan test delivery, time-division multiplexing, TDM
CITATION
John Mark Nolen, Rabi N. Mahapatra, "Time-Division-Multiplexed Test Delivery for NoC Systems", IEEE Design & Test of Computers, vol.25, no. 1, pp. 44-51, January-February 2008, doi:10.1109/MDT.2008.27
REFERENCES
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5. J.M. Nolen and R. Mahapatra, "A TDM Test Scheduling Method for Network-on-Chip Systems," Proc. 6th Int'l Workshop Microprocessor Test and Verification (MTV 05), IEEE CS Press, 2005, pp. 90—98.
6. E.J. Marinissen, V. Iyengar, and K. Chakrabarty, "A Set of Benchmarks for Modular Testing of SOCs," Proc. Int'l Test Conf. (ITC 02), IEEE CS Press, 2003, pp. 519—528.
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