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Decreasing Test Qualification Time in AMS and RF Systems
January-February 2008 (vol. 25 no. 1)
pp. 29-37
ASCII Text
x 
 
Yves Joannon, Vincent Beroulle, Chantal Robach, Smail Tedjini, Jean-Louis Carbonéro, "Decreasing Test Qualification Time in AMS and RF Systems," IEEE Design & Test of Computers, vol. 25, no. 1, pp. 29-37, January-February, 2008.
 
 
BibTex
x
 
@article{ 10.1109/MDT.2008.7,
author = {Yves Joannon and Vincent Beroulle and Chantal Robach and Smail Tedjini and Jean-Louis Carbonéro},
title = {Decreasing Test Qualification Time in AMS and RF Systems},
journal ={IEEE Design & Test of Computers},
volume = {25},
number = {1},
issn = {0740-7475},
year = {2008},
pages = {29-37},
doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2008.7},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - MGZN
JO - IEEE Design & Test of Computers
TI - Decreasing Test Qualification Time in AMS and RF Systems
IS - 1
SN - 0740-7475
SP29
EP37
EPD - 29-37
A1 - Yves Joannon,
A1 - Vincent Beroulle,
A1 - Chantal Robach,
A1 - Smail Tedjini,
A1 - Jean-Louis Carbonéro,
PY - 2008
KW - fault-based test
KW - qualification
KW - design validation
KW - AMS and RF SoCs
KW - VHDL-AMS
KW - behavioral modeling
KW - parametric fault injection
VL - 25
JA - IEEE Design & Test of Computers
ER -
 
Yves Joannon, Grenoble Institute of Technology
Vincent Beroulle, Grenoble Institute of Technology
Chantal Robach, Grenoble Institute of Technology
Smail Tedjini, Grenoble Institute of Technology
Jean-Louis Carbonéro, STMicroelectronics
The test cost of heterogeneous ICs has significantly increased. So, the definition of relevant test methods and efficient test stimuli are becoming critical research orientations for semiconductor manufacturers. The authors of this article propose decreasing the manufacturing test cost of analog and mixed-signal (AMS) and RF SoCs by automatically qualifying and optimizing the existing test set. Their computer-aided test (CAT) tool, Plasma, uses fault injection and a fault simulation technique to perform test qualification and generation. This tool reduces both test time and test equipment cost using a high-level fault model. After discussing the advantages using behavioral fault models, the authors present a method that lets them decrease overall simulation time. This method reduces the number of simulated fault-free models, thanks to a normal estimation.

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Index Terms:
fault-based test, qualification, design validation, AMS and RF SoCs, VHDL-AMS, behavioral modeling, parametric fault injection
Citation:
Yves Joannon, Vincent Beroulle, Chantal Robach, Smail Tedjini, Jean-Louis Carbonéro, "Decreasing Test Qualification Time in AMS and RF Systems," IEEE Design & Test of Computers, vol. 25, no. 1, pp. 29-37, Jan.-Feb. 2008, doi:10.1109/MDT.2008.7
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