This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Decreasing Test Qualification Time in AMS and RF Systems
January-February 2008 (vol. 25 no. 1)
pp. 29-37
Yves Joannon, Grenoble Institute of Technology
Vincent Beroulle, Grenoble Institute of Technology
Chantal Robach, Grenoble Institute of Technology
Smail Tedjini, Grenoble Institute of Technology
Jean-Louis Carbonéro, STMicroelectronics
The test cost of heterogeneous ICs has significantly increased. So, the definition of relevant test methods and efficient test stimuli are becoming critical research orientations for semiconductor manufacturers. The authors of this article propose decreasing the manufacturing test cost of analog and mixed-signal (AMS) and RF SoCs by automatically qualifying and optimizing the existing test set. Their computer-aided test (CAT) tool, Plasma, uses fault injection and a fault simulation technique to perform test qualification and generation. This tool reduces both test time and test equipment cost using a high-level fault model. After discussing the advantages using behavioral fault models, the authors present a method that lets them decrease overall simulation time. This method reduces the number of simulated fault-free models, thanks to a normal estimation.

1. A. Palaniswamy, A. Jayasumana, and Y.K. Malaiya, "A Neural Network Based Approach for Testing Analog Circuits with Frequency Domain Classification and Time Domain Testing," Proc. IEEE Int'l System Test Diagnosis Workshop, IEEE Press, 1999, http://www.engr.colostate.edu/ece/faculty/ jayasumana/pdf/conferencessyststdgnosis_99_ap.pdf .
2. K. Saab, N. Ben-Hamida, and B. Kaminska, "Parametric Fault Simulation and Test Vector Generation," Proc. IEEE Conf. Design, Automation and Test in Europe Conf. (DATE 00), IEEE CS Press, 2000, pp. 650—657.
3. A. Bounceur et al., "A CAT Platform for Analog and Mixed-Signal Test Evaluation and Optimization," Proc. IEEE European Test Conf., IEEE Press, 2006, pp. 217—222.
4. F. Liu and S. Ozev, "Fast Hierarchical Process Variability Analysis and Parametric Test Development for Analog/RF Circuits," Proc. IEEE Int'l Conf. Computer Design (ICCD 05), IEEE CS Press, 2005, pp. 161—170.
5. E. Acar and S. Ozev, "Parametric Test Development for RF Circuits Targeting Physical Fault Locations and Using Specification-Based Fault Definitions," Proc. IEEE/ACM Int'l Conf. Computer-Aided Design (ICCAD 05), IEEE CS Press, 2005, pp. 73—79.
6. R.L. Wardrop, "Normal Quantile Plots and Statistical Inference," Dept. of Statistics, Univ. of Wisconsin-Madison, 1 Mar. 1999, pp. 1—5, http://www.stat.wisc.edu/∼wardrop/ paperstr1008.pdf.
7. J.-M Jolion, "Probabilités et Satistique [Probabilities and Statistics]," July 2001, http://rfv.insa-lyon.fr/∼jolion/STAT poly.html (in French).
8. Y. Joannon et al., "Behavioral Modeling of WCDMA Transceivers with VHDL-AMS Language," Proc. IEEE Conf. Design and Diagnostics of Electronics Circuits and Systems, IEEE CS Press, 2007, pp. 111—116.
9. C. Force, "Analog Fault Simulation: Key to Product Quality, or a Foot in the Door," Proc. Int'l Test Conf. (ITC 99), IEEE CS Press, 1999, p. 650.
10. Y. Joannon et al., "Choice of a High Level Fault Model for the Optimization of Validation Test Set Reused for Manufacturing Test," Proc. IEEE Int'l Mixed-Signals Testing Workshop (IMSTW 07), IEEE Press, 2007, pp. 62—67.
1. V. Natarajan et al., "Novel Cross-Loopback Based Test Approach for Specification Test of Multi-band, Multi-hardware Radios," Proc. IEEE VLSI Test Symp., IEEE CS Press, 2007, pp. 297—302.
2. A. Palaniswamy, A. Jayasumana, and Y.K. Malaiya, "A Neural Network Based Approach for Testing Analog Circuits with Frequency Domain Classification and Time Domain Testing," Proc. IEEE Int'l System Test Diagnosis Workshop, IEEE Press, 1999, http://www.engr.colostate.edu/ece/faculty/ jayasumana/pdf/conferencessyststdgnosis_99_ap.pdf
3. K. Saab, N. Ben-Hamida, and B. Kaminska, "Parametric Fault Simulation and Test Vector Generation," Proc. IEEE Conf. Design, Automation, and Test in Europe (DATE 2000), IEEE CS Press, 2000, pp. 650—657.
4. A. Bounceur et al., "A CAT Platform for Analogue and Mixed-Signal Test Evaluation and Optimization," Proc. IFIP Int'l Conf. Very Large Scale Integration, IEEE Press, 2006, pp. 320—325.
5. Y. Joannon et al., "Choice of a High Level Fault Model for the Optimization of Validation Test Set Reused for Manufacturing Test," Proc. IEEE Int'l Mixed-Signals Testing Workshop (IMSTW 07), IEEE Press, 2007, pp. 62—67.
6. M.W. Tian and C.-JR. Shi, "Worst Case Tolerance Analysis of Linear Analog Circuits Using Sensitivity Bands," IEEE Trans. Circuits and Systems, vol. 47, no. 8, Aug. 2000, pp. 1138—1145.

Index Terms:
fault-based test, qualification, design validation, AMS and RF SoCs, VHDL-AMS, behavioral modeling, parametric fault injection
Citation:
Yves Joannon, Vincent Beroulle, Chantal Robach, Smail Tedjini, Jean-Louis Carbonéro, "Decreasing Test Qualification Time in AMS and RF Systems," IEEE Design & Test of Computers, vol. 25, no. 1, pp. 29-37, Jan.-Feb. 2008, doi:10.1109/MDT.2008.7
Usage of this product signifies your acceptance of the Terms of Use.