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Aegis: A Single-Chip Secure Processor
November-December 2007 (vol. 24 no. 6)
pp. 570-580
ASCII Text
x 
 
G. Edward Suh, Charles W. O'Donnell, Srinivas Devadas, "Aegis: A Single-Chip Secure Processor," IEEE Design & Test of Computers, vol. 24, no. 6, pp. 570-580, November-December, 2007.
 
 
BibTex
x
 
@article{ 10.1109/MDT.2007.179,
author = {G. Edward Suh and Charles W. O'Donnell and Srinivas Devadas},
title = {Aegis: A Single-Chip Secure Processor},
journal ={IEEE Design & Test of Computers},
volume = {24},
number = {6},
issn = {0740-7475},
year = {2007},
pages = {570-580},
doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2007.179},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - MGZN
JO - IEEE Design & Test of Computers
TI - Aegis: A Single-Chip Secure Processor
IS - 6
SN - 0740-7475
SP570
EP580
EPD - 570-580
A1 - G. Edward Suh,
A1 - Charles W. O'Donnell,
A1 - Srinivas Devadas,
PY - 2007
KW - Aegis
KW - secure processor
KW - architecture
KW - single chip
KW - FPGA
VL - 24
JA - IEEE Design & Test of Computers
ER -
 
G. Edward Suh, Cornell University
Charles W. O'Donnell, Massachusetts Institute of Technology
Srinivas Devadas, Massachusetts Institute of Technology
This article presents the Aegis secure processor architecture, which enables physically secure computing platforms with a main processor as the only trusted component. The Aegis architecture ensures private and authentic program execution even in the face of physical attacks, using two new security primitives. First, physical unclonable functions (PUFs) generate cryptographic keys in a highly secure yet inexpensive manner, exploiting random manufacturing variations. Second, off-chip memory protection mechanisms ensure the integrity and privacy of off-chip memory. Aegis, with its new protection mechanisms, has been implemented on an FPGA, and is fully functional. The authors briefly assess the cost of the security mechanisms in the Aegis processor and show that it is reasonable.

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Index Terms:
Aegis, secure processor, architecture, single chip, FPGA
Citation:
G. Edward Suh, Charles W. O'Donnell, Srinivas Devadas, "Aegis: A Single-Chip Secure Processor," IEEE Design & Test of Computers, vol. 24, no. 6, pp. 570-580, Nov.-Dec. 2007, doi:10.1109/MDT.2007.179
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