Issue No.06 - November-December (2007 vol.24)
G. Edward Suh , Cornell University
Charles W. O'Donnell , Massachusetts Institute of Technology
Srinivas Devadas , Massachusetts Institute of Technology
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2007.179
This article presents the Aegis secure processor architecture, which enables physically secure computing platforms with a main processor as the only trusted component. The Aegis architecture ensures private and authentic program execution even in the face of physical attacks, using two new security primitives. First, physical unclonable functions (PUFs) generate cryptographic keys in a highly secure yet inexpensive manner, exploiting random manufacturing variations. Second, off-chip memory protection mechanisms ensure the integrity and privacy of off-chip memory. Aegis, with its new protection mechanisms, has been implemented on an FPGA, and is fully functional. The authors briefly assess the cost of the security mechanisms in the Aegis processor and show that it is reasonable.
Aegis, secure processor, architecture, single chip, FPGA
G. Edward Suh, Charles W. O'Donnell, Srinivas Devadas, "Aegis: A Single-Chip Secure Processor", IEEE Design & Test of Computers, vol.24, no. 6, pp. 570-580, November-December 2007, doi:10.1109/MDT.2007.179