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Secured CAD Back-End Flow for Power-Analysis-Resistant Cryptoprocessors
November-December 2007 (vol. 24 no. 6)
pp. 546-555
ASCII Text
x 
 
Sylvain Guilley, Florent Flament, Philippe Hoogvorst, Renaud Pacalet, Yves Mathieu, "Secured CAD Back-End Flow for Power-Analysis-Resistant Cryptoprocessors," IEEE Design & Test of Computers, vol. 24, no. 6, pp. 546-555, November-December, 2007.
 
 
BibTex
x
 
@article{ 10.1109/MDT.2007.202,
author = {Sylvain Guilley and Florent Flament and Philippe Hoogvorst and Renaud Pacalet and Yves Mathieu},
title = {Secured CAD Back-End Flow for Power-Analysis-Resistant Cryptoprocessors},
journal ={IEEE Design & Test of Computers},
volume = {24},
number = {6},
issn = {0740-7475},
year = {2007},
pages = {546-555},
doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2007.202},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - MGZN
JO - IEEE Design & Test of Computers
TI - Secured CAD Back-End Flow for Power-Analysis-Resistant Cryptoprocessors
IS - 6
SN - 0740-7475
SP546
EP555
EPD - 546-555
A1 - Sylvain Guilley,
A1 - Florent Flament,
A1 - Philippe Hoogvorst,
A1 - Renaud Pacalet,
A1 - Yves Mathieu,
PY - 2007
KW - robust hardware
KW - back-end design automation
KW - power-constant architectures
KW - side-channel attacks
KW - mitigation
KW - DFM
KW - DFY
VL - 24
JA - IEEE Design & Test of Computers
ER -
 
Sylvain Guilley, École Nationale Supérieure des Télécommunications
Florent Flament, Hewlett-Packard
Philippe Hoogvorst, Centre National de la Recherche Scientifique
Renaud Pacalet, École Nationale Supérieure des Télécommunications
Yves Mathieu, École Nationale Supérieure des Télécommunications
This article presents a comprehensive back-end design flow that enables the realization of constant-power cryptoprocessors, natively protected against side-channel attacks exploiting the instant power consumption. The proposed methodology is based on a fully custom-balanced cell library and an innovative place-and-route method. This article shows that it is indeed possible to implement hardware that is robust against all known power attacks. All the design steps involved in this methodology take place at the layout level. The described flow has been applied to the quasi-delay-insensitive SecLib library with a shielded routing method derived from back-end duplication, using legacy CAD tools for the back-end steps. The authors evaluate the cost of the secured methodology through an example of a multimode DES datapath.

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Index Terms:
robust hardware, back-end design automation, power-constant architectures, side-channel attacks, mitigation, DFM, DFY
Citation:
Sylvain Guilley, Florent Flament, Philippe Hoogvorst, Renaud Pacalet, Yves Mathieu, "Secured CAD Back-End Flow for Power-Analysis-Resistant Cryptoprocessors," IEEE Design & Test of Computers, vol. 24, no. 6, pp. 546-555, Nov.-Dec. 2007, doi:10.1109/MDT.2007.202
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