This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Power Analysis Attacks and Countermeasures
November-December 2007 (vol. 24 no. 6)
pp. 535-543
Thomas Popp, Graz University of Technology
Stefan Mangard, Infineon Technologies
Elisabeth Oswald, University of Bristol
One of the biggest challenges of designers of cryptographic devices is to protect the devices against implementation attacks. Power analysis attacks are among the strongest of these attacks. This article provides an overview of power analysis attacks and discusses countermeasures against them. In particular, this article summarizes recent results with countermeasures that can be implemented at the cell level. Many countermeasures of this kind have been proposed, but several limitations of these countermeasures have been identified.

1. P.C. Kocher, J. Jaffe, and B. Jun, "Differential Power Analysis," Proc. 19th Ann. Int'l Cryptology Conf. Advances in Cryptology: (CRYPTO 99), LNCS 1666, Springer-Verlag, 1999, pp. 388-397.
2. S. Mangard, E. Oswald, and T. Popp, Power Analysis Attacks: Revealing the Secrets of Smart Cards, Springer, 2007.
3. S. Chari, J.R. Rao, and P. Rohatgi, "Template Attacks," Proc. 4th Int'l Workshop Cryptographic Hardware and Embedded Systems (CHES 02), LNCS 2523, Springer, 2003, pp. 13-28.
4. "FIPS-197: Advanced Encryption Standard," Nat'l Inst. of Standards and Technology, Nov. 2001; http://www.itl.nist.govfipspubs.
5. J.J.A. Fournier et al., "Security Evaluation of Asynchronous Circuits," Proc. 5th Int'l Workshop Cryptographic Hardware and Embedded Systems (CHES 03), LNCS 2779, Springer, 2003, pp. 137-151.
6. K. Tiri, M. Akmal, and I. Verbauwhede, "A Dynamic and Differential CMOS Logic with Signal Independent Power Consumption to Withstand Differential Power Analysis on Smart Cards," Proc. 28th European Solid-State Circuits Conf. (ESSCIRC 02), IEEE Press, 2002, pp. 403-406.
7. T. Popp and S. Mangard, "Masked Dual-Rail Pre-Charge Logic: DPA-Resistance without Routing Constraints," Proc. 7th Int'l Workshop Cryptographic Hardware and Embedded Systems (CHES 05), LNCS 3659, Springer, 2005, pp. 172-186.
8. S. Mangard, T. Popp, and B.M. Gammel, "Side-Channel Leakage of Masked CMOS Gates," Proc. Topics in Cryptology: Cryptographers' Track at RSA Conf. (CT-RSA 05), LNCS 3376, Springer, 2005, pp. 351-365.
9. D. Suzuki and M. Saeki, "Security Evaluation of DPA Countermeasures Using Dual-Rail Pre-charge Logic Style," Proc. 8th Int'l Workshop Cryptographic Hardware and Embedded Systems (CHES 06), LNCS 4249, Springer, 2006, pp. 255-269.
10. K. Tiri and P. Schaumont, "Changing the Odds against Masked Logic," Proc. 13th Int'l Workshop Selected Areas in Cryptography (SAC 2006), LNCS 4356, Springer, 2007, http://rijndael.ece.vt.edu/schaum/papers 2006sac.pdf.
1. O. Kömmerling and M.G. Kuhn, "Design Principles for Tamper-Resistant Smartcard Processors," Proc. Usenix Workshop Smartcard Technology (Smartcard 99), Usenix Assoc, 1999, pp. 9-20.
2. S.P. Skorobogatov, "Semi-Invasive Attacks: A New Approach to Hardware Security Analysis," doctoral dissertation, Computer Lab., Univ. of Cambridge, 2005, http://www.cl.cam.ac.ukTechReports.

Index Terms:
power analysis attacks, countermeasures, DPA-resistant logic styles
Citation:
Thomas Popp, Stefan Mangard, Elisabeth Oswald, "Power Analysis Attacks and Countermeasures," IEEE Design & Test of Computers, vol. 24, no. 6, pp. 535-543, Nov.-Dec. 2007, doi:10.1109/MDT.2007.200
Usage of this product signifies your acceptance of the Terms of Use.