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Issue No.06 - November-December (2007 vol.24)
pp: 516
Published by the IEEE Computer Society
ABSTRACT
The design of secure and trusted embedded systems has recently drawn enormous attention from system-design practitioners. A secure system is only as strong as the weakest link. Therefore, any security functions implemented in an embedded system must be considered in both hardware and software, at all design abstraction levels, in communications between components, and in the manufacturing phase. In addition, these implementations are subject to typical power, performance, and cost constraints of consumer embedded systems. This issue of IEEE Design & Test features a special issue on Design and Test of Integrated Circuits for Secure Embedded Computing.
The design of secure and trusted embedded systems has recently drawn enormous attention from system-design practitioners. As is commonly known, a secure system is only as strong as the weakest link. Thus, any security functions implemented in an embedded system must be considered in both hardware and software, at all design abstraction levels, in communications between components, and in the manufacturing phase. In addition, these implementations are subject to typical power, performance, and cost constraints of consumer embedded systems. Although there are publications dedicated to security issues (for example, IEEE Security & Privacy magazine), most of these emphasize software aspects and lack in-depth treatment of hardware-related concerns—especially chip design.
Therefore, the IEEE Design & Test editorial board decided to publish a special issue on Design and Test of Integrated Circuits for Secure Embedded Computing. Six articles, selected from a large pool of high-quality submissions, examine various issues within secure embedded-systems design. Topics include a comprehensive survey and comparison of state-of-the-art cryptography implementations for embedded systems; an overview of side-channel attacks and countermeasures against such attacks; a hardware design flow that considers resistance to side-channel attacks; a mixed hardware-software approach for balancing security and performance of cryptographic computations; a single-chip, secure processor architecture and its associated design considerations; and the software and hardware architecture of ARM's TrustZone technology. In addition to these articles, this special issue also includes four sidebars, written by industry and academic experts, offering complementary viewpoints on this theme. I'd like to take this opportunity to thank Guest Editors Patrick Schaumont and Anand Raghunathan for their great job in putting together this very strong, exciting issue.
Thanks to digital-edition-delivery technologies and the desire to reach a broader audience of practitioners, D&T has begun offering its content in electronic format (beginning with the May–June 2007 issue). The digital editions are mirror images of the print copies and can be read and stored online or printed out for future reference. Such an offering provides instant, convenient access to cutting-edge research results and enables global technology practitioners to avoid international mailing delays. For more information and for subscription details, please go to http://www.qmags.com/magazines/PubHomePage.asp?publication=129.




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