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X-Tolerant Compactor with On-Chip Registration and Signature-Based Diagnosis
September-October 2007 (vol. 24 no. 5)
pp. 476-485
Jerzy Tyszer, Poznań University of Technology
Janusz Rajski, Mentor Graphics
Grzegorz Mrugalski, Mentor Graphics
Nilanjan Mukherjee, Mentor Graphics
Mark Kassab, Mentor Graphics
Wu-Tung Cheng, Mentor Graphics
Manish Sharma, Mentor Graphics
Liyang Lai, Mentor Graphics
This article presents a two-stage test response compactor with scan selection logic and an on-chip compare-and-response collector. This compactor is capable of handling a wide range of X state profiles, offers compression far higher than the ratio of scan chains to compactor outputs, and provides excellent diagnostic resolution.

4761. S. Mitra, S.S. Lumetta, and M. Mitzenmacher, "X-Tolerant Signature Analysis," Proc. Int'l Test Conf. (ITC 04), IEEE CS Press, 2004, pp. 432–441.
1. S. Mitra, S.S. Lumetta, and M. Mitzenmacher, "X-Tolerant Signature Analysis," Proc. Int'l Test Conf. (ITC 04), IEEE CS Press, 2004, pp. 432–441.
2. J.H. Patel, S.S. Lumetta, and S.M. Reddy, "Application of Saluja-Karpovsky Compactors to Test Responses with Many Unknowns," Proc. 21st IEEE VLSI Test Symp. (VTS 03), IEEE CS Press, 2003, pp. 107–112.
3. C. Barnhart et al., "Extending OPMISR beyond 10 ×Scan Test Efficiency," IEEE Design &Test, vol. 19, no. 5, Sept.-Oct. 2002, pp. 65–73.
4. J. Rajski et al., "Embedded Deterministic Test," IEEE Trans. Computer-Aided Design, vol. 23, no. 5, May 2004, pp. 776–792.
5. P. Wohl et al., "X-Tolerant Compression and Application of Scan-ATPG Patterns in a BIST Architecture," Proc. Int'l Test Conf. (ITC 03), IEEE CS Press, 2003, pp. 727–736.
6. Y. Tang et al., "X-Masking during Logic BIST and Its Impact on Defect Coverage," Proc. Int'l Test Conf. (ITC 03), IEEE CS Press, 2003, pp. 442–451.
7. V. Chickermane, B. Foutz, and B. Keller, "Channel Masking Synthesis for Efficient On-Chip Test Compression," Proc. Int'l Test Conf. (ITC 04), IEEE CS Press, 2004, pp. 452–461.
8. M. Naruse et al., "On-Chip Compression of Output Responses with Unknown Values Using LFSR Reseeding," Proc. Int'l Test Conf. (ITC 03), IEEE CS Press, 2003, pp. 1060–1068.
9. F. Poehl et al., "On-Chip Evaluation, Compensation, and Storage of Scan Diagnosis Data—A Test Time Efficient Scan Diagnosis Architecture," Proc. 11th European Test Symp. (ETS 06), IEEE CS Press, 2006, pp. 239–246.
10. J. Rajski et al., "X-Press Compactor for 1000 ×Reduction of Test Data," Proc. Int'l Test Conf. (ITC 06), IEEE CS Press, 2006, art. 297643 (10 pp.).
11. D. Czysz et al., "New Test Data Decompressor for Low Power Applications," Proc. 44th Design Automation Conf. (DAC 07), ACM Press, 2007, pp. 539–544.
12. W.-T Cheng et al., "Signature Based Diagnosis for Logic BIST," Proc. Int'l Test Conf. (ITC 06), IEEE CS Press, 2006, art. 297720 (9 pp.).
13. T. Bartenstein et al., "Diagnosing Combinational Logic Designs Using the Single Location At-a-Time (SLAT) Paradigm," Proc. Int'l Test Conf. (ITC 01), IEEE CS Press, 2001, pp. 287–296.

Index Terms:
DFT, embedded test, fault diagnosis, on-chip collection of test data, scan-based designs, selective compaction of test responses
Citation:
Jerzy Tyszer, Janusz Rajski, Grzegorz Mrugalski, Nilanjan Mukherjee, Mark Kassab, Wu-Tung Cheng, Manish Sharma, Liyang Lai, "X-Tolerant Compactor with On-Chip Registration and Signature-Based Diagnosis," IEEE Design & Test of Computers, vol. 24, no. 5, pp. 476-485, Sept.-Oct. 2007, doi:10.1109/MDT.2007.177
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