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Issue No.05 - September-October (2007 vol.24)
pp: 454-463
Steve B. Furber , University of Manchester
Steve Temple , University of Manchester
Mukaram Khan , University of Manchester
Yebin Shi , University of Manchester
Luis A. Plana , University of Manchester
Shufan Yang , University of Manchester
ABSTRACT
The Spinnaker (Spiking Neural Network Architecture) system for large-scale neural modeling is based on a scalable processor chip containing multiple ARM cores. Using a globally asynchronous, locally synchronous (GALS) approach allows custom, off-the-shelf IP to be readily integrated without significant timing-closure design effort. The ARM processors are used to simulate neurons, and generated neural events are carried over an on-chip, packet-switched fabric. This self-timed interconnect is also extended off chip to a provide chip-to-chip interconnect that scales to networks of thousands of chips.
INDEX TERMS
massively parallel multiprocessor, GALS, Spinnaker, neural modeling, self-timed interconnect
CITATION
Steve B. Furber, Steve Temple, Mukaram Khan, Yebin Shi, Luis A. Plana, Shufan Yang, "A GALS Infrastructure for a Massively Parallel Multiprocessor", IEEE Design & Test of Computers, vol.24, no. 5, pp. 454-463, September-October 2007, doi:10.1109/MDT.2007.149
REFERENCES
1. S. Furber and S. Temple, "Neural Systems Engineering," J. Royal Society Interface, vol. 4, no. 13, Apr. 2007, pp. 193–206.
2. J. Bainbridge and S. Furber, "Chain: A Delay-Insensitive Chip Area Interconnect," IEEE Micro, vol. 22, no. 5, Sept.-Oct. 2002, pp. 16–23.
3. T. Verhoeff, "Delay-Insensitive Codes—An Overview," Distributed Computing, vol. 3, no. 1, Mar. 1988, pp. 1–8.
4. Silistix Self-Timed Interconnect Technology, Silistix; http://www.silistix.comtechnology_silistix.php .
5. Advanced Microcontroller Bus Architecture (AMBA) Specification, Rev. 2.0, ARM, May 1999, http://www.arm.com/products/solutionsAMBAHomePage.html .
6. W.J. Bainbridge et al., "Delay-Insensitive, Point-to-Point Interconnect Using M-of-N Codes," Proc. 9th IEEE Int'l Symp. Asynchronous Circuits and Systems (ASYNC 03), IEEE CS Press, 2003, pp. 132–140.
7. J. Wu and S. Furber, "Delay Insensitive Chip-to-Chip Interconnect Using Incomplete 2-of-7 NRZ Data Encoding," Proc. 18th UK Asynchronous Forum, University of Newcastle upon Tyne, 2006, pp. 16–19, http://async.org.ukukasyncforum18/.
8. Y. Shi and S. Furber, "Error Checking and Resetting Mechanisms for Asynchronous Interconnect," Proc. 18th UK Asynchronous Forum, University of Newcastle upon Tyne, 2006, pp. 24–27, http://async.org.uk/ukasyncforum18.
9. ARM968E-S, ARM, http://www.arm.com/products/CPUsARM968E-S.html .
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