Issue No.05 - September-October (2007 vol.24)
Mike Kishinevsky , Intel
Sandeep K. Shukla , Virginia Tech
Kenneth S. Stevens , University of Utah
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2007.166
Globally asynchronous, locally synchronous (GALS) design has grown in popularity in both academia and industry. Breaking the synchrony assumption in digital design is often unsettling for designers, and to alleviate the difficulty, researchers in EDA have been proposing various GALS-based solutions. However, the tools, verification techniques, and testing methodologies for asynchronous designs are not as widespread as for synchronous digital design, leading to the hitherto limited usage of GALS design approaches. This special issue introduces some of the basic issues of GALS design and validation in the hardware domain. The hope is that this special issue will generate more interest by researchers and industry practitioners in creating design tools, techniques, and validation methodologies for GALS design.
synchronous, asynchronous, design, validation
Mike Kishinevsky, Sandeep K. Shukla, Kenneth S. Stevens, "Guest Editors' Introduction: GALS Design and Validation", IEEE Design & Test of Computers, vol.24, no. 5, pp. 414-416, September-October 2007, doi:10.1109/MDT.2007.166