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Issue No.05 - September-October (2007 vol.24)
pp: 412
ABSTRACT
Globally asynchronous, locally synchronous (GALS) design is emerging as the architecture of choice for certain applications. In a GALS system, the circuitry in each timing domain is locally synchronized, and different clock domains are glued together according to asynchronous communication schemes. This issue of IEEE Design & Test introduces some basic design and validation issues of the GALS architecture. The editorial from the guest editors outlines the scope of this special theme. In addition to the special theme, this issue also includes a special section highlighting the International Test Conference (ITC). Finally, there is a short report of highlights from the 2007 Design Automation Conference held earlier this year.
INDEX TERMS
synchronous, asynchronous, ITC, high-performance systems, DAC
CITATION
Tim Cheng, "Combining synchronous and asynchronous timing schemes for high-performance systems", IEEE Design & Test of Computers, vol.24, no. 5, pp. 412, September-October 2007, doi:10.1109/MDT.2007.158
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