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Leakage Minimization Technique for Nanoscale CMOS VLSI
July/August 2007 (vol. 24 no. 4)
pp. 322-330
ASCII Text
x 
 
Kyung Ki Kim, Yong-Bin Kim, Minsu Choi, Nohpill Park, "Leakage Minimization Technique for Nanoscale CMOS VLSI," IEEE Design & Test of Computers, vol. 24, no. 4, pp. 322-330, July/August, 2007.
 
 
BibTex
x
 
@article{ 10.1109/MDT.2007.141,
author = {Kyung Ki Kim and Yong-Bin Kim and Minsu Choi and Nohpill Park},
title = {Leakage Minimization Technique for Nanoscale CMOS VLSI},
journal ={IEEE Design & Test of Computers},
volume = {24},
number = {4},
issn = {0740-7475},
year = {2007},
pages = {322-330},
doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2007.141},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - MGZN
JO - IEEE Design & Test of Computers
TI - Leakage Minimization Technique for Nanoscale CMOS VLSI
IS - 4
SN - 0740-7475
SP322
EP330
EPD - 322-330
A1 - Kyung Ki Kim,
A1 - Yong-Bin Kim,
A1 - Minsu Choi,
A1 - Nohpill Park,
PY - 2007
KW - nanometer CMOS
KW - cell characterization
KW - leakage power
KW - subthreshold leakage current
KW - gate-tunneling current
KW - input pattern generation
VL - 24
JA - IEEE Design & Test of Computers
ER -
 
Kyung Ki Kim, Northeastern University
Yong-Bin Kim, Northeastern University
Minsu Choi, University of Missouri-Rolla
Nohpill Park, Oklahoma State University, Stillwater
This article proposes a new heuristic approach to determine the input patterns that minimize leakage currents of nanometer CMOS circuits during sleep mode. The proposed approach uses a new macromodeling technique to characterize the minimum leakage current of each individual cell, considering fan-out effects, stack effect, and the interaction between gate-leakage and subthreshold currents. Experimental results shows that the methodology using the proposed macromodel provides less than a 4% error compared to Hspice simulation results.
Index Terms:
nanometer CMOS, cell characterization, leakage power, subthreshold leakage current, gate-tunneling current, input pattern generation
Citation:
Kyung Ki Kim, Yong-Bin Kim, Minsu Choi, Nohpill Park, "Leakage Minimization Technique for Nanoscale CMOS VLSI," IEEE Design & Test of Computers, vol. 24, no. 4, pp. 322-330, July-Aug. 2007, doi:10.1109/MDT.2007.141
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