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Tracking Uncertainty with Probabilistic Logic Circuit Testing
July/August 2007 (vol. 24 no. 4)
pp. 312-321
| ASCII Text | x | ||
| Smita Krishnaswamy, Igor L. Markov, John P. Hayes, "Tracking Uncertainty with Probabilistic Logic Circuit Testing," IEEE Design & Test of Computers, vol. 24, no. 4, pp. 312-321, July/August, 2007. | |||
| BibTex | x | ||
| @article{ 10.1109/MDT.2007.146, author = {Smita Krishnaswamy and Igor L. Markov and John P. Hayes}, title = {Tracking Uncertainty with Probabilistic Logic Circuit Testing}, journal ={IEEE Design & Test of Computers}, volume = {24}, number = {4}, issn = {0740-7475}, year = {2007}, pages = {312-321}, doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2007.146}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - MGZN JO - IEEE Design & Test of Computers TI - Tracking Uncertainty with Probabilistic Logic Circuit Testing IS - 4 SN - 0740-7475 SP312 EP321 EPD - 312-321 A1 - Smita Krishnaswamy, A1 - Igor L. Markov, A1 - John P. Hayes, PY - 2007 KW - probabilistic faults KW - logic circuit testing KW - integer linear programming KW - fault-modeling framework KW - test-vector sensitivity VL - 24 JA - IEEE Design & Test of Computers ER - | |||
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2007.146
Probabilistic faults are increasingly affecting logic circuits in the nanometer realm. Examples include transients caused by cosmic radiation, randomness in quantum and nanocircuits, and process variability in manufacturing. The authors of this article generalize the variations caused by these faults to the notion of a probabilistic fault model. They then delineate the differences between these faults and the more traditional deterministic faults. Such effects require a reformulation of testing and test-generation methods. In particular, the same fault can be detected by several test vectors, with varying probabilities. The authors call the probability that a test vector detects a fault its "sensitivity" to the fault. They propose test generation methods for probabilistic faults with the goal of bounding and estimating fault probabilities. Finally, the authors propose a fault-modeling framework for efficient representation of probabilistic faults, algorithms to compute test-vector sensitivity, and integer linear programming (ILP) to generate compact test sets with high probabilities of coverage.
Index Terms:
probabilistic faults, logic circuit testing, integer linear programming, fault-modeling framework, test-vector sensitivity
Citation:
Smita Krishnaswamy, Igor L. Markov, John P. Hayes, "Tracking Uncertainty with Probabilistic Logic Circuit Testing," IEEE Design & Test of Computers, vol. 24, no. 4, pp. 312-321, July-Aug. 2007, doi:10.1109/MDT.2007.146
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