Circuit activity is a function of input patterns. When circuit activity changes abruptly, it can cause a sudden drop or rise in power supply voltage. This change is known as power droop and is an instance of power supply noise. Although power droop can cause an IC to fail, such failures cannot currently be screened during testing because they are not covered by conventional fault models. This article presents a technique for screening such failures. The authors propose a heuristic method to generate test sequences that create worst-case power drop by accumulating the high- and low-frequency effects. The authors employ a dynamically constrained version of the classical D-algorithm, which generates new constraints on the fly, for test generation. The obtained patterns can be used for manufacturing testing as well as for early silicon validation. The authors have implemented a prototype ATPG to demonstrate the feasibility of this approach, and they generate test sequences for ISCAS circuits.