Issue No.03 - May-June (2007 vol.24)
Praveen Ghanta , Arizona State University
Sarma Vrudhula , Arizona State University
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2007.61
This article presents a comprehensive methodology for analyzing the impact of device and metal process variations on the power supply noise and hence the signal integrity of on-chip power grids. This approach models the power grid using modified nodal-analysis equations, and is based on representing the voltage response as an orthogonal polynomial series in the process variables. The series is truncated, and coefficients of the series are optimally obtained by using the Galerkin method. The authors thus obtain an analytical representation of the voltage response in the process variables that can be directly sampled to obtain the voltage response at different process corners. The authors have verified their analysis exhaustively on several industrial power grids as large as 1.3 million nodes, and considering up to 20 process variables. Results from their method demonstrate a very good match with those from Monte Carlo simulations, while providing significant speedups of the order of 100 to 1,000 times for comparable accuracy.
modeling methodologies, computer-aided design, power supply noise, verification, voltage response, process variations
Praveen Ghanta, Sarma Vrudhula, "Analysis of Power Supply Noise in the Presence of Process Variations", IEEE Design & Test of Computers, vol.24, no. 3, pp. 256-266, May-June 2007, doi:10.1109/MDT.2007.61