Power integrity is emerging as a major challenge in SoC designs in deep-submicron (DSM) technologies. Existing design and analysis techniques and metrics fail to provide an accurate impact estimation of power supply noise, making it difficult to optimize design and test procedures. The lack of predictability is complicating timing closure, physical design, production test, and speed-grading of SoCs. Furthermore, traditional power supply noise reduction techniques are not capable of addressing some of the new issues that have arisen in DSM. This article describes and validates two metrics that quantify the impact of power supply noise. The authors propose modified decoupling-capacitor (decap) designs and present results of silicon experimentation. They also discuss the true impact of power supply noise on production test, and present DFT techniques to reduce power supply noise during testing.