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A Survey of Hybrid Techniques for Functional Verification
March-April 2007 (vol. 24 no. 2)
pp. 112-122
Jayanta Bhadra, Freescale Semiconductor
Magdy S. Abadir, Freescale Semiconductor
Li-C. Wang, University of California, Santa Barbara
Sandip Ray, University of Texas at Austin
The increasing size and complexity of industry hardware designs, along with stringent time-to-market requirements, have put a heavy burden on verification to ensure that designs are relatively bug free. A general theme successfully adopted by academia and several vendors is to apply multiple verification techniques so that they complement one another, resulting in an increase of the verification tool's overall effectiveness. Such integration must be carried out delicately and precisely so that the overall technique becomes more than merely a sum of the techniques. This article surveys the research that has taken place in this area.
Index Terms:
functional verification, hybrid, formal techniques, informal techniques
Citation:
Jayanta Bhadra, Magdy S. Abadir, Li-C. Wang, Sandip Ray, "A Survey of Hybrid Techniques for Functional Verification," IEEE Design & Test of Computers, vol. 24, no. 2, pp. 112-122, March-April 2007, doi:10.1109/MDT.2007.30
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