• How do we design new reliable products with enhanced environmental awareness? In the field of test, design and subsequent test have given way to DFT techniques. Consequently, system dependability has driven the need for online testing for transient faults such as single-event upsets (SEU). It might be possible to reuse such on-chip resources for design for EMC (DF_EMC). The design, test, and EMC communities need to work together to minimize the cost of DF_EMC.
• How can we predict system reliability in early design stages? IC designers should consider emission and susceptibility models for IP-core simulation and soft-error rate (SER) prediction when purchasing such products from core providers.
• How effective are existing test procedures and standards at bringing such systems to the market? New standards and test procedures should scale down to 65-nm technology ICs running under clock rates far beyond 1 GHz. In this arena, IC designers should consider using EM direct coupling with ICs rather than conducted coupling at the board level toward the IC input pins.