Issue No.06 - November/December (2006 vol.23)
Published by the IEEE Computer Society
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2006.148
With increased technology scaling, high variability and low reliability will likely be the main challenges for chip design and testing. This issue discusses some of the key issues for handling increasing variations and uncertainties. Also, D&T's plans for 2007 special themes have been finalized.
Drastic device shrinking, lower power supply levels, and increasing operating speeds significantly reduce noise margins and increase variations in process, device, and design parameters. These trends lead to lower reliability and higher design uncertainty for hardware components. With further technology scaling, high variability and low reliability are bound to become the predominant challenges for chip design and testing.
It's not just technology that incurs increasing variations. The environment, energy, thermal resources, and even applications have larger variations, making hardware design even more challenging. Given these variations, worst-case design will be way too conservative, if not impossible. Statistical design, or better-than-worst-case design, will be a viable solution for further pushing the design envelope. However, such a shift in the fundamental design principle will introduce new challenges to test because then a component could fail to meet specifications even without containing a defect. The test process will need to screen out components that fall in the tail end of the distributions for certain process, device, and design parameters. This is a very challenging task.
In addition, to increase product reliability and product yield, we'll need new solutions that will let the hardware adapt after fabrication, or even after deployment in the field, to cope with such variations and uncertainties. Some people predict that we'll soon need to adopt a new design and test paradigm that will assume unreliable building blocks must be used to design reliable systems. Actually, such a concept has already been employed in advanced systems in avionic and automotive applications. What is new is the introduction of these technologies into the consumer domain, where cost has been a serious constraint.
This issue of IEEE Design & Test discusses some of the key issues for handling these increasing variations and uncertainties. Our guest editors, T.M. Mak and Sani Nassif, have selected five interesting articles and a Last Byte column that address these issues from several different perspectives. Their guest editorial explains the motivation for featuring this special theme and contains a brief summary of each article. I would like to take this opportunity to thank T.M. and Sani for their great job in putting together this strong issue.
D&T's plans for 2007 special theme issues have been finalized. The topics covered by these special issues will include biochips; functional validation; IR-drop and power supply noise effects; ultra high-speed networks; and globally asynchronous, locally synchronous design and test. We are now soliciting proposals for special themes for issues to be published in 2008. If you are interested in acting as a guest editor for a theme issue, please provide your special issue topic proposals for evaluation by our editorial board. Please see our Web site ( http://www.computer.org/dt) for guidelines on submitting individual manuscripts and theme issue proposals.
I hope you will enjoy the articles in this special issue on process variation and stochastic design and test. We welcome your feedback.
Editor in Chief
IEEE Design & Test