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Issue No.05 - September/October (2006 vol.23)
pp: 426-427
Published by the IEEE Computer Society
Scott Davidson , Sun Microsystems
ABSTRACT
A review of Electronic Design Automation for Integrated Circuits Handbook, edited by Louis Scheffer, Luciano Lavagno, and Grant Martin.
In the November–December 2004 Last Byte, I bemoaned the fact that design has become so complex that no one person can understand all of it, and that EDA tools have become so diverse and complicated that we confine ourselves to a small subset of their functionality. The massive book under review here, Electronic Design Automation for Integrated Circuits Handbook, represents the best way I know to address this problem.
This two-volume set contains 49 articles on EDA, ranging from high-level design to technology CAD. The first volume, EDA for IC System Design, Verification, and Testing, has five sections: An introductory section outlines and summarizes the design process. A section on system-level design discusses modeling languages, processor and system modeling, performance metrics, and system-level power management. The microarchitectural design section describes performance estimation, power management, and design planning at this level. Six chapters on logic verification cover design and verification languages, and various verification methods. The final section, on test, focuses on DFT, test generation, and analog test.
The second volume, EDA for IC Implementation, Circuit Design, and Process Technology, focuses on the second part of the IC design flow. It includes sections on synthesis, place and route, analog and mixed-signal design, physical verification, and technology CAD. Chapters within these sections cover topics such as synthesis, power management at all levels, design rule checking, design for manufacturability, timing analysis, noise analysis, and libraries.
I confess that I did not read all the chapters in this book, wishing to complete the review before we move to biochips. In fact, when I first received this text, I was certain that I'd never finish it. But I'm not so sure now. I have already read more chapters than I'd originally intended, and I think the reason for this explains why this handbook is a success. In most cases, the material covers the important points without going into so much detail or length as to be intimidating. Chapters range from seven pages to 33 pages, with an average of 15 to 20, each including an extensive list of references. This seemed just right for the surveys making up this handbook. You cannot completely learn EDA from a book like this, of course, but you can learn quite a lot about EDA.
There are three types of chapters throughout the book. Some are introductory in nature, surveying a topic such as design flow at a high level. Some target EDA users, showing the types of tools that are available and putting them into context. Others target EDA developers, describing the algorithms underlying the tools, with information on the benefits of each. Some subjects are covered from several angles. Most subjects could be, of course, but that would balloon this work into three or four volumes. For the most part, I was happy with the choice of angle; only in a few cases, such as the chapter on design rule checking, would I have preferred a more user-oriented approach.
One danger of a handbook approach is repetition, as important subjects tend to get covered more than once. However, I found very little redundancy in this book. There was practically none in the sections on test. The editors must have done an excellent job reviewing chapter outlines.
The most important thing, though, is how good the individual chapters are. So, I will give my impressions of some of the ones I read. The first full chapter is "The Integrated Design Process and Electronic Design Automation." This chapter starts a bit abruptly, but quickly progresses into an excellent overview of the design process. I'd recommend it to everyone who reads these volumes. I wish it had some pointers to subsequent chapters, however. Chapter 5, "SoC Block-Based Design and IP Assembly," is an excellent tutorial focusing on real issues, especially in the area of verification.
Chapter 8, "Processor Modeling and Design Tools," provides a taxonomy and survey of architecture description languages (ADLs). The taxonomy is excellent, describing very clearly what ADLs are and what they are not. However, I would have liked to see more of an industrial focus in the survey. This chapter had a bit more of an academic slant than most of the others. The chapter on "Design and Verification Languages," on the other hand, covers commercially available languages with excellent examples. An outline gives the salient points of each language, with strong points and weak points, and includes a taste of how to do coding in each language. At 28 pages, this is one of the longer chapters, but hardly a word is wasted.
There are three chapters on test, two of which I'd like to discuss here. Chapter 21, "Design-for-Test," is one of the longest (35 pages) in the book. It contains even more text than the page count indicates, in fact, because it includes absolutely no figures or diagrams. This chapter covers a lot, from the objectives and history of DFT; through scan, BIST, and compression for logic testing; to memory test. It ends with a short section on FPGA test (which could easily have been cut). The reader of this chapter might have a hard time distinguishing which of these concepts are truly important and which are minor. In addition, there is often too much detail for an introductory survey. For example, there is almost an entire page in the section on logic BIST about structural dependencies and scan chain lengths. These are issues, but they could have been eliminated to make the chapter shorter and more readable. The chapter on "Automatic Test Pattern Generation" is more developer oriented, with a survey of ATPG algorithms. It's somewhat academic, with a large section on Boolean satisfiability (SAT) solvers for test generation, but this is balanced by an excellent section on applications for ATPGs beyond test generation.
The chapter on "Logic Synthesis" (in volume 2) is 15 pages and has 11 references. It gives a very high-level view of a well-known subject. I think the author was right to avoid trying to cover all aspects of this area in depth, instead pointing the reader to places for further study. Chapter 6, "Static Timing Analysis," is one of the best chapters I read. It is at the right length and depth, and it provides helpful pseudocode for the major algorithms discussed. Chapter 9, "Exploring Challenges of Libraries for Electronic Design," considers not cell libraries, but IP libraries. At eight pages, it is very short and superficial. The last three subsections are basically only outlines.
The last chapter I want to highlight is the one on "Design Databases." This chapter is excellent. It targets users, but displays a deep knowledge of the implementations of design databases. It is also very readable.
Conclusion
Every design group should have a copy of this handbook in its library. It is an excellent reference text. It can also serve as outstanding background reading for new engineers exposed to some of these areas for the first time. The material here is better organized and better written than what could be found on the Web. Putting together such a high-quality, substantive work is quite an achievement. I'll be reading more chapters for quite some time to come.
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