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Issue No.05 - September/October (2006 vol.23)
pp: 414-424
Sebasti? A. Bota , University of the Balearic Islands
Josep L. Rossell? , University of the Balearic Islands
Carol de Benito , University of the Balearic Islands
Jaume Segura , University of the Balearic Islands
ABSTRACT
It is a well-known phenomenon that test-mode switching activity and power consumption can exceed that of mission mode. Thus, testing can induce localized heating and temperature gradients with deleterious results. The authors quantify this problem and propose a novel design scheme to circumvent it.
INDEX TERMS
clock skew, clock distribution network, temperature, interconnect delay
CITATION
Sebasti? A. Bota, Josep L. Rossell?, Carol de Benito, Ali Keshavarzi, Jaume Segura, "Impact of Thermal Gradients on Clock Skew and Testing", IEEE Design & Test of Computers, vol.23, no. 5, pp. 414-424, September/October 2006, doi:10.1109/MDT.2006.126
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