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Issue No.05 - September/October (2006 vol.23)
pp: 333
Published by the IEEE Computer Society
ABSTRACT
This issue of IEEE Design & Test discusses some of the challenges of electronic system-level design and their corresponding solutions. In addition, a special section highlights the 2006 International Test Conference.
Designers are hungry for electronic system-level (ESL) methodologies and supporting tools that can raise the abstraction level of design entry and enhance the global analysis and exploration of design trade-offs. A recent report by Gartner Dataquest on worldwide EDA market trends forecasted a strong growth rate for ESL tools over the next five years. However, existing solutions remain inadequate, and a comprehensive ESL design infrastructure brings with it several challenges that design and test professionals must solve. This issue of IEEE Design & Test discusses some of these challenges and their corresponding solutions. Guest editors Sandeep Shukla, Carl Pixley, and Gary Smith have collected a set of interesting articles concerning languages, tools, and methodologies of ESL design. I'd like to thank them for the great job they've done in putting together this strong issue.
In addition, we are happy to present a special section highlighting the 2006 International Test Conference (ITC). In the sub-65-nanometer technology era, in which electronic products encounter a far wider variety of failure sources and a higher failure rate than ever, test has gradually expanded its role in the semiconductor industry. Test is no longer limited to defect detection. It has become a critical technology for debugging, yield improvement, and design for reliability as well. This trend inspired this year's ITC theme, "Getting More out of Test." Guest editor Ken Butler, 2005 ITC program chair, has selected three articles for this special section that highlight this theme.
We also have some exciting plans for the next few issues of D&T. Special-issue themes will include important industry topics such as process variation and stochastic design and test, biochips, functional validation, and IR drop and power supply noise effects on design and test. We will also present exciting roundtables, such as the one moderated by Andrew Kahng at the 43rd Design Automation Conference (DAC 06), on design and tool challenges for next-generation multimedia, game, and entertainment platforms. In addition, at the 6th International Forum on Application-Specific MultiProcessor SoC (MPSoC 06), Roundtables editor Bill Joyner moderated a roundtable on single-chip multiprocessor architectures, which we will include in a future issue of D&T. You will also see interesting interviews with key technologists, such as Texas Instruments' Hans Stork, keynote speaker at this year's DAC.
If you'd like to participate in a future D&T issue, please submit your theme or nontheme manuscript as soon as it is ready. To serve as a guest editor, submit your special-issue proposal for evaluation by the D&T editorial board. See D&T's Web site ( http://computer.org/dt) for guidelines. For additional information or clarification, please feel free to contact me directly.




Kwang-Ting (Tim) Cheng
Editor in Chief
IEEE Design & Test
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