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Issue No.04 - July/August (2006 vol.23)
pp: 318-319
Published by the IEEE Computer Society
Sachin Sapatnekar , University of Minnesota
ABSTRACT
A review of Leakage in Nanometer CMOS Technologies, edited by Siva G. Narendra and Anantha Chandrakasan (Springer, 2006).
One of the most significant consequences of technology scaling is the "leaky tap" syndrome. From the early '80s until recently, an "off" transistor in a CMOS circuit had been correctly modeled as an open circuit, but from the 130-nm technology node downward, this assumption has broken down; now, even a transistor that is purportedly "off" leaks current.
Moreover, this is a growing problem whose severity increases rapidly as feature sizes shrink. At the scale of an individual transistor, the magnitude of leakage current is negligible. Multiply this inconsequential drip per transistor by the millions or billions of transistors on a chip, however, and the problem becomes a serious nuisance and a major stumbling block in design. In fact, leakage throws a wrench into the very justification for deploying CMOS technologies in the '80s, when the rationale for replacing the current technologies was that the static-power dissipation of a CMOS circuit was essentially zero. This is no longer true.
Although persisting with CMOS still has its advantages, the very survival of this technology depends on finding plumbing techniques to understand and design around the leaky tap. Leakage in Nanometer CMOS Technologies describes the issues in detail through an introduction and 11 chapters written by a group of leading high-performance circuit designers.
Leakage basics
The book begins with an overview of the basics of leakage—the sources and the expected trends—and then launches into a more detailed exploration of the area. Chapter 2 begins at the gate level and explains how stacking the transistors in a particular manner can affect the leakage and how this leads to design techniques that depart from conventional methods.
Next, Chapters 3 and 4 present two perspectives on methods, such as power gating and dynamic voltage scaling, predominantly applied at higher levels of abstraction. Here, the content weaves skillfully between the block level and the transistor level to provide a complete view of design considerations. These chapters introduce the basic idea of power gating, where Vdd is shut off to a block of gates. This is followed by an explanation of how to use multithreshold CMOS (MTCMOS) sleep devices for power gating at several levels, ranging from the gate level to the macrocell level or block level. The chapters address practical issues, such as clustering circuitry that shares sleep transistors, interfacing between sleep regions (to overcome potential problems when power gating creates nodes that can "float" at arbitrary voltage levels), and designing MTCMOS latches.
Chapter 4 ends with a quick introduction to dynamic voltage scaling and subthreshold circuit design, describing several industrial cases including an NTT communication chip, a Samsung PDA processor, and a Toshiba DSP core for a cell phone design. Although EDA tools do not widely support this style as yet, the chapter describes some initial offerings on the market.
Chapter 5 discusses an alternative approach to controlling leakage. As the authors point out, reverse body biases have been used in memory chips since the mid-1970s because of latchup considerations, but it is only in the past few years that the method has found gainful use for power optimization. The chapter begins with a clear exposition of reverse body bias, using a self-adjusting threshold voltage scheme, and is followed by a discussion on variable threshold CMOS (VTCMOS) circuit designs and forward body-bias techniques. It also includes an analysis of the effects of technology scaling effects on using body-biasing techniques in deeply scaled nanometer technologies.
Next, Chapter 6 addresses process variations on design performance and how to compensate for the effects of these variations using adaptive body biases and adaptive supply voltages. The use of this method permits a design to recover to its desired performance levels through postsilicon tuning.
Accounting for leakage
For many chips, memories constitute a significant portion of silicon area and, consequently, a major potential source of leakage losses. Chapter 7 covers SRAM- and DRAM-specific leakage reduction techniques, including considerations in the transistor-level design of SRAM and DRAM cells as well as peripheral circuitry.
Next, Chapter 8 addresses logic circuits, where, in addition to standby leakage, leakage during the active mode of computation is also becoming a significant fraction of the total losses. The chapter presents techniques for dynamic power gating, the application of dynamic body biases, and multi- Vt devices for active power control. Aside from normal modes of operation—that is, in the active and standby modes—leakage is a significant contributor to power dissipation during manufacturing test, particularly under stress conditions such as burn-in test. Chapter 9 thoroughly describes leakage power issues in burn-in test, as well as some solutions.
Chapters 10 and 11 move on to specific microprocessor case studies from Hitachi/Renesas and Intel. These chapters provide an overview of how to bring together the isolated techniques from the previous chapters, considering system-level trade-offs, to build a commercial product.
Finally, Chapter 12 discusses engineering transistors specifically for leakage reduction, providing an outline of cutting-edge methods in this domain and some promising ideas for the future.
Conclusion
Leakage in nanometer CMOS technologies provides thorough coverage, but, as often happens in an edited volume, some ideas are repeated and the level of coherence is somewhat diffused. Although explaining some ideas more than once can be a good thing—the exposition of these ideas from different authors with different backgrounds tends to provide a more complete view and reinforce important concepts—the organization of the book could have benefited from just a little more coordination between the chapters. Consecutive chapters sometimes jump from one topic to another, while apparently connected topics are many chapters apart. That said, these complaints are minor. A reader who wishes to learn about leakage in depth will read the entire book and absorb all the ideas that it provides.
In an area that is rapidly changing and will continue to do so in the coming years, Leakage in Nanometer CMOS Technologies throws in everything but the kitchen sink. To the best of my knowledge, no other single source covers these topics, and the editors and the chapter authors have provided the community with a valuable resource: an excellent and in-depth view of the state of the art. This book can also be a useful reference for the next generation of researchers, as well as practitioners in circuit design and EDA, as they learn to live with the annoyance of leaky taps and apply their ingenuity to overcoming the problem—perhaps even by leveraging leakage and viewing it as a virtue rather than a liability.
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