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Issue No.04 - July/August (2006 vol.23)
pp: 315
Published by the IEEE Computer Society
Ajay Khoche , Agilent
ABSTRACT
A report on the IEEE VLSI Test Symposium (VTS 06) panel on "Real-time volume diagnostics: requirements and challenges.
Ajay Khoche
Agilent
Organizer: A. Khoche, Agilent; moderator: P. Muhmenthaler, Infineon
Panelists: D. Apello, STMicroelectronics; I. Hartanto, Avago Technologies; T. Jackson, Cadence; W.T. Cheng, Mentor Graphics; and T. Williams, Synopsys
THE IEEE VLSI Test Symposium (VTS 06), which took place in Berkeley, California, 30 April–4 May, featured numerous special sessions, including panels, embedded tutorials, and hot topic presentations.
The panel on "Real-time volume diagnostics: requirements and challenges" discussed developing an environment to enable volume diagnostics. As we move along the technology nodes into the nanometer era, the initial and mature yield drop and the distribution of the yield detractor changes to include a large proportion of defects due to systematic design and process interactions. Simulating such a mechanism for prediction and avoidance is computationally very complex for any chips of a reasonable size. This forces us to identify such defects on the real silicon in production over a large volume using volume diagnostics. This panel confirmed the need for production-enabled diagnosis and identified the following as requirements and challenges:

    No or low throughput impact: It is essential that such a system minimally affects the test floor's throughput to an extent justifiable by the returns in the yield. This would involve ATE improvements.

    Scalable and efficient storage and compute infrastructure: Such storage and infrastructure enables logging and analyzing large amounts of data with extreme automation to handle multiple tools and flows.

    Accuracy: The diagnosis tools should be able to identify the failing cell, layer, bridges, and scan-chains and interconnect with high accuracy. ATE should allow accurate data capture as well.

    DFT support: The diagnosis tools should be able to diagnose failures using the outputs available from the compression structures placed on the chip. In addition, diagnosis tools should be interoperable over the DFT structures being placed by tools from other EDA vendors.

    Standard for data logging format: In the presence of multiple ATE and EDA vendors, a standard data-logging format is need to enable smooth information flow from ATEs to diagnosis tools.

    Correlation to other monitoring data: It is essential to correlate the volume diagnostics data with data obtained from other yield-monitored processes, such as in-line inspection, and provide necessary data-mining tools to create defect models and to handle the complex yield issues.

Conclusion
The panel and audience also discussed the current state of the tools and agreed that the tools necessary to implement high-accuracy volume diagnostics might not be ready—for example, there is no diagnosis for failure due to signal integrity. Automatic test pattern generation tools still focus on screening, which needs to change. In addition, the panel also discussed the ownership of deploying such volume diagnostic systems and concluded that a multiparty partnership using standard data formats is the right way to implement such a system.
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