Issue No.04 - July/August (2006 vol.23)
Published by the IEEE Computer Society
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2006.108
A popular DATE keynote speaker and an award-winning author are among the contributors to this issue, which covers on-chip testing, the sociology of EDA, quiescent-signal analysis, and a survey of test vector compression techniques.
This issue of IEEE Design & Test features a very popular keynote address from a recent top-tier conference: Mentor Graphics CEO Wally Rhines's keynote address from DATE '06.
The speech, titled "Sociology of Design and EDA," stressed the increasingly important requirements of bidirectional information flow among design, test, and EDA specialists as they successfully design complex electronic systems. However, such specialists are becoming more dispersed geographically and organizationally, making effective communication among them more challenging. Rhines outlines how such requirements affect the necessary design-flow types, the nature of design tools, the way design software is supported, and the organizational structure in the EDA and electronics industries.
I would like to thank Rhines for giving D&T readers access to the data and vision presented at his keynote address.
The problem of rapid growth in test data volume for testing complex ICs has made test data compression a very active research and development area in recent years. This issue includes a survey article by Nur Touba on test vector compression. In addition to a comprehensive survey of various test-vector compression techniques, this article offers great insights into trade-offs and how these techniques are related to each other.
We also include an article based on the IEEE TTTC 2005 Best Doctoral Thesis Award. The article—based on Valdes-Garcia's PhD thesis developed at Texas A&M University—describes a set of on-chip techniques for testing an entire wireless RF transceiver system (as well as its major building blocks) without using off-chip analog or RF instrumentation.
Increasing leakage current has made single-threshold IDDQ testing obsolete and ineffective for identifying defective parts. As an enhanced defect detection and diagnosis technique, quiescent-signal analysis that uses IDDQ measurements at multiple chip supply ports helps reduce the leakage component in each measurement. It also improves detection of subtle defects. The article by Plusquellic et al. applies statistical analysis to data collected from test chips to evaluate this technique.
I thank all the authors and associate editors who contributed to this issue. I hope you enjoy it. If you have any feedback, please share it with us.
Kwang-Ting (Tim) Cheng
Editor in Chief
IEEE Design & Test