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System-in-Package Testing: Problems and Solutions
May/June 2006 (vol. 23 no. 3)
pp. 203-211
Davide Appello, STMicroelectronics
Paolo Bernardi, Politecnico di Torino
Michelangelo Grosso, Politecnico di Torino
Matteo Sonza Reorda, Politecnico di Torino
Editor's note: System-in-package integrates multiple dies in a common package. Therefore, testing SiP technology is different from system-on-chip, which integrates multiple vendor parts. This article provides test strategies for known-good-die and known-good-substrate in the SiP. Case studies provefeasibility using the IEEE 1500 test structure.
Index Terms:
System-on-Chip, System-on-Package, System-in-Package, SiP, SoC, test access mechanism, IEEE1500 SECT, KGD
Citation:
Davide Appello, Paolo Bernardi, Michelangelo Grosso, Matteo Sonza Reorda, "System-in-Package Testing: Problems and Solutions," IEEE Design & Test of Computers, vol. 23, no. 3, pp. 203-211, May-June 2006, doi:10.1109/MDT.2006.79
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