Issue No.03 - May/June (2006 vol.23)
Published by the IEEE Computer Society
Sachin Sapatnekar , University of Minnesota
Grant Martin , Tensilica
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2006.66
The 43rd Design Automation Conference presents leading-edge industry practices and academic research across IC, embedded-systems, and "beyond the die" design technologies and methodologies. The authors discuss the highlights, from keynote talks by reknowned personalities in the semiconductor industry to hands-on tutorials.
This year's 43rd Design Automation Conference presents leading-edge industry practices and academic research across IC, embedded-systems, and "beyond the die" design technologies and methodologies. Receiving a record 865 submissions to DAC 2006—an increase of 15 percent over 2005—the technical program committee comprised more than 80 members. As cochairs of the technical program, we worked with the committee as they reviewed and selected papers for the program, drawing on the expertise of hundreds of external reviewers as well.
Two keynote talks by eminent personalities in the semiconductor industry will headline DAC 2006, which will be held on 24–28 July in San Francisco. On Tuesday, Hans Stork from Texas Instruments will discuss the technical issues in designing future mobile communication design, factoring in technology scaling, process, and design challenges. On Thursday, Alessandro Cremonesi from STMicroelectronics will present an insider's perspective on the challenges of convergence and the complexity of system-level integration at the system, embedded software, and silicon implementation levels.
Special theme: multimedia, games, and entertainment
For 2006, DAC's theme is multimedia, games, and entertainment: the design challenges and design technology requirements for creating advanced products in this product area. Events in the technical program and on the exhibit floor will reflect this issue, and will be highlighted on Wednesday, 26 July. The themed track on this day opens with a special session highlighting the best papers in multimedia from the International Solid-State Circuits Conference, with presentations from Renasas/DoCoMo, MediaTek, National Chiao-Tung University, and Samsung. It continues with an invited session on CAD challenges for leading-edge multimedia designs followed by a panel on design challenges for next-generation multimedia, games, and entertainment platforms. These two sessions include experts from STMicroelectronics, IBM, ATI, nVidia, PixelWorks, Qualcomm, and Intel. Finally, a regular paper session will feature the best submissions on power-constrained design for multimedia.
Complementing the theme sessions, pavilion panels will take place on the exhibit floor throughout the week. These include panels on "Inside the iPod and PSP," technology requirements for 3D graphics in feature films, and challenges encountered in the design of the Xbox 360.
Technical paper presentations
The technical program is divided into 10 tracks: management; system-level and embedded-systems design; low power; analog and circuit; interconnect, reliability, and design for manufacturability (DFM); verification and test; synthesis and FPGA; physical design; "beyond the die"; and new and emerging technologies.
A new track highlights design challenges beyond individual IC design to its packaging and incorporation into higher levels of design and interconnection at the system level. This includes a paper session and a key technologies special session with experts from Rio Design Automation, IBM, Brown University, and University of California, Berkeley. Another new track focuses on new technologies, with three sessions—including nanotechnologies and bio-chip design—exposing the leading technologies' possible design challenges in the next few years.
The management track includes a business panel on the fabless model, as well as one session on the choice of flows and implementation technologies and another session on design of graphics, entertainment, and wireless products.
Among the largest tracks at DAC 2006 are system-level and embedded design (with 10 sessions) and verification and test (with another 10). System-level design also saw the largest growth in paper submissions in 2006. The use of processors in more and more system-on-chip (SoC) designs and a focus on on-chip interconnect and communications-centric design, including network-on-chip, are strong themes this year. Optimizing software for real-time considerations and taking power and memory use into account are the most important criteria in embedded software. Transaction-level modeling is an interesting trend at the system level that also flows into detailed implementation and verification. In the verification area, we also see a focus on processor-centric verification. Another strong theme this year is verification planning—moving from formal specifications through well-defined verification processes to achieve satisfactory coverage and quality. Finally, aspects of formal verification continue to be an active area of research and continued progress in design adoption, and a session on bounded-model checking and equivalence verification and another on simulation-assisted formal verification will bring researchers and practitioners up-to-date with the latest work.
DFM continues to attract impressive work to be show-cased in the technical program. Sessions will address the newest developments in statistical timing and power analysis methods, design-technology interactions, practical issues in DFM, and yield analysis and improvement. In the area of low-power design, the DAC program has several sessions that discuss issues from low-power, thermally aware architectures to circuit-level low-power design and analysis. Research results on signal integrity, physical design, and reliability issues—solving the newest problems generated by technology scaling—also form a significant chunk of the program, with sessions on topics such as power grid design, routing and buffer insertion, and soft error mitigation.
Besides these topics, many others—such as analog circuit design and CAD, logic and high-level synthesis, and FPGA/reconfigurable circuit issues—figure prominently in the schedule.
Special sessions and panels
The DAC technical program also includes a set of panels and special sessions. Special sessions are invited groups of presentations that highlight important issues that will likely interest the DAC audience. This year's panels cover the front end, back end, and issues in between. At the front end, the sessions will address issues such as multiprocessor system-on-chip (MPSoC) design and maintaining consistency between verification at the system-level transaction-level models and register-transfer level (RTL) models. Back-end sessions will cover reliability issues in sub-65-nm technologies, postsilicon debug, and beyond-the-die design, which will particularly interest circuit designers and EDA professionals. Two forward-looking sessions will address environmental energy harvesting for ultra-low-power systems and industry-driven perspectives on post-CMOS technologies.
DAC's panel sessions fall into two classes: the pavilion panels presented in the exhibit area and the program panels in the technical program. The 16 pavilion panels are, broadly speaking, more business oriented and are relatively informal and flexible. Topics this year include an "Ask the CTO" panel, a Dataquest-driven EDA trends panel, and a discussion on the US$4 billion revenue barrier for the EDA industry. The program panels have more educational themes and invite panelists with diverse views to discuss contemporary issues. This year's list includes panels on DFM, the fabless model's viability, verification issues, thermal problems, electronic system-level (ESL) design, analog issues, and nanoscale design. The panelists are a distinguished group of leaders in the field and are certain to provide ample food for thought.
As in the past few years, DAC will offer two flavors of tutorials: hands-on tutorials, exposing designers to real tools and flows around a theme, and full-day tutorials typically built around presenting new concepts and ideas and intended to be more broadly educational. This year's hands-on tutorials are based on low-power design, and their scope spans six to eight sets of design tools and flows that specifically target various design abstraction levels from the system level to physical implementation.
The full-day tutorials will be held on Monday, 24 July, and Friday, 28 July. DFM and ESL design and verification are represented by two tutorials each—one on Monday and one on Friday—so attendees interested in these two hot areas could attend a tutorial in each area. The DFM tutorials cover practical aspects of coping with variability, and industry-driven presentations on real DFM solutions, tools, methodologies, and successes. The two ESL tutorials cover SystemC transaction-level models through several use cases and an in-depth tutorial on using SystemVerilog. In addition, other tutorial topics include issues in chip-package codesign (in keeping with DAC's new beyond-the-die initiative), postsilicon error diagnosis, and silicon debug and defect diagnosis.
DAC will repeat the popular Sunday workshop on Unified Modeling Language (UML) and SoC design. Organized by John Wolfe and Yves Vanderperren, this workshop continues to build the links between DAC and embedded systems and software design.
For more details on DAC, including registration information, please visit http://www.dac.com.
Sachin Sapatnekar is the Henle professor of Electrical and Computer Engineering at the University of Minnesota, and technical program (tools) cochair of this year's DAC. Contact him at firstname.lastname@example.org.
Grant Martin is chief scientist of Tensilica Inc. and technical program (methods) cochair of this year's DAC. Contact him at email@example.com.