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Issue No.02 - March/April (2006 vol.23)
pp: 168-171
Published by the IEEE Computer Society
Kartikeya Mayaram , Oregon University
ABSTRACT
A newsletter for the newly formed IEEE Council on Electronic Design Automation.
Welcome to the inaugural newsletter of the IEEE Council on Electronic Design Automation!
Kartikeya Mayaram, Oregon State University
D&T takes this opportunity to introduce the mission and goals of IEEE CEDA. Why CEDA? Certainly, EDA as a subject area—from monolithic circuits to large information processing systems—has been spread across many technical activities within the IEEE. Within the context of electronic systems, when CAD started as a discipline in the 1960s, it was synonymous with circuit simulation. Now, of course, CAD deals with a much broader set of concerns that continue to evolve with the technological advances in materials, processing, devices, circuits, and systems generally put under the umbrella of electronic design automation. On one side of the spectrum, the physical design of electronic circuits requires a deep knowledge of solid-state circuits and, more broadly, electronic devices. On the other side, the ubiquitous presence of programmable processor cores in ICs has shifted much CAD work into the design of embedded software and hardware-software codesign—areas traditionally covered by computer scientists. Indeed, combining theory and practice, CAD is a key technology that boasts its own thriving industry as well as being an enabler for the much larger electronic-systems industry.
So it was natural for such an activity to have a diversified footprint within the IEEE as a technical organization. Although this diversity of CAD activities within the IEEE benefited the larger EDA community with significant cross-fertilization of ideas, this diversity made it much harder for the IEEE to serve the community with necessary, timely information and publications reflecting advances in EDA. Significant EDA-related forums—the Design Automation Conference (DAC), the International Conference on Computer Aided Design (ICCAD), IEEE Transactions on CAD, and IEEE Design & Test of Computers—though highly regarded, were often deemed as secondary activities within the respective societies. This made it difficult to recognize volunteer achievements and execute initiatives that demanded participation across different parts of the IEEE.
To ensure IEEE responsiveness to a technical community of more than 5,000 active members, a working group of EDA industry and academic leaders gathered in early 2004. Their goal was to build a focal point that would be instrumental in supporting a vision of growth and renewal within the IEEE and its Technical Activities Board. Working with a broad set of partners, the working group polled and conferred with all interested societies and councils within the IEEE to build the consensus for an organization that was officially approved, first as an ad hoc committee in June 2004, and finally ratified as a council effective January 2006.
Within IEEE Technical Activities, a council represents an organization with member societies. IEEE CEDA has six member societies: Antennas and Propagation, Circuits and Systems, Computer, Electron Devices, Microwave Theory and Techniques, and Solid-State Circuits. As with any technical area within the IEEE, CEDA's ultimate goal is to advance the profession through various technical activities, such as conferences, publications, and standards. To serve its members, who are spread across various member societies, CEDA brings together several important resources: its community of contributors, sponsored conferences, and publications. As of this writing, cosponsored conferences include DAC, ICCAD, and Design and Test in Europe (DATE). In addition, CEDA copublishes IEEE Transactions on CAD and IEEE Design & Test of Computers, and it enjoys special relationships with focused technical activities such as the Design Automation Technical Committee (DATC), the Test Technology Technical Council (TTTC), and the Computer-Aided Network Design (CANDE) committee.
With founding societies as members, what does it mean for an individual to be a member of CEDA? CEDA does not have official members in the sense that the IEEE associates members with dues (paid to the societies). Instead, individuals can sign up as friends of IEEE CEDA. This helps the emerging council move forward in building the community initiatives without being bogged down by issues associated with membership dues and their division across IEEE entities. The key to success for this formulation is the enormous support IEEE CEDA has received from its sponsoring societies.
IEEE CEDA's inaugural kickoff took place at ICCAD in November 2005. The meeting included presentations and endorsements from the founding societies within the IEEE, the Special Interest Group on Design Automation (SIGDA) of the ACM, and the Electronic Design Automation Consortium (EDAC). CEDA's founders are pleased to receive such broad support and community momentum toward building the council. We are also humbled by the challenges facing the community in continuing to build at the pace of innovation in semiconductors. To do so, we must rapidly attract new talent and entrepreneurship to the field, to engender technical activities that excite and challenge our audience and readership, spurring them on to new capabilities and opportunities. The diversity of the contributors' backgrounds also demands council processes that encourage consensus building. In the very first few months, CEDA converged on areas of technical interest, as well as constitutions and bylaws that were unanimously adopted by the founding members. It has now initiated several technical activities, including sponsorship of the first IEEE Programming Challenge to take place at the International Workshop on Logic Synthesis, as well as participation in the DARPA Microsystems Technology Office (MTO) activities around building a roadmap for electronic systems. This newsletter briefly describes both activities.
This is a promising start of what we hope will be exciting years of innovation and invention in EDA! These activities are possible only through our constituent membership's participation. So get involved! if you have an idea or a suggestion, or if you are looking for a challenge in organizing a technical activity, workshop, symposium, publication, or standard, please look us up at http://www.ieee-ceda.org, or contact any of the volunteer leaders in the respective areas, and, of course, remember to sign on as a friend of IEEE CEDA!
CEDA sponsors first IEEE programming contest
Stephen Edwards, Columbia University
CEDA will sponsor a programming challenge for the first time in the history of the International Workshop for Logic Synthesis (IWLS), which will take place 7 to 9 June 2006 near Denver, Colo. The goal is to build and foster a new open-source logic synthesis system that will provide the base for future comprehensive EDA tool flows. The event's long-term goal is to build a complete RTL-to-layout implementation flow that also includes physical synthesis and optimization steps. CEDA encourages Individuals as well as teams of students to participate in this challenge to either implement their current research on this platform or to implement known and published synthesis algorithms as part of their education. For students who want to participate but lack concrete ideas, CEDA will soon publish a list of suggested algorithms to implement.
The challenge is to implement one or more logic optimization algorithms on the industrial EDA database Open Access. The algorithms should make maximum use of the Open Access database, be implemented in a native manner, and adhere to Open Access coding conventions. The algorithm should be implemented within the Open Access Gear infrastructure (see description at http://www.iwls.org/challenge). Open Access Gear provides

    • an RTL-Verilog reader and its synthesis into a technology-independent netlist (an AND-inverter graph or AIG),

    • a simple mapper that directly maps the nodes of the AIG onto a specified set of three library elements (AND, NOT, or flip-flop),

    • accurate timing analysis with slew propagation, and

    • a simple equivalence checker based on the AIG representation.

The technology-dependent optimization algorithms should be implemented directly on Open Access and should use the functional layer (package Func) in Open Access Gear together with the AIG package. Participants should evaluate the results of the technology-dependent algorithms by performing accurate timing analysis and, preferably, using the incremental timing analysis of the Open Access Gear timer.
Prizes include a travel grant as well as a cash prize of $500. Only full-time students registered during the spring 2006 semester are eligible to participate. The winners will be invited to either give a talk or present a poster as part of the workshop program. The submission deadline for the two-page technical paper is 15 April 2006, and the deadline for the source code is 1 May 2006 (midnight PST). For more information, go to http://www.iwls.org/challenge/.
CEDA participates in 2006 DARPA Electronics Symposium
The charter of DARPA's MTO is to "exploit breakthroughs in materials, devices, circuits, and mathematics to develop beyond leading-edge components with revolutionary performance and functionality to enable new platform capability for the Department of Defense." Practically, DARPA charges the MTO with programs related to the field of integrated electronics and its ecosystem, including photonics, microelectromechanical systems, and EDA. MTO programs constitute a good fraction of the approximate $0.5 billion in material and electronics R&D (split evenly) that DARPA spends annually. These include many programs of direct interest to the CEDA community such as 3D integrated circuits, chip-to-chip optical interconnects, clockless logic, distributed macro-electronics, and the Focus Center Research Program. The latter supports initiatives such as the Gigascale Systems Research Center at the University of California, Berkeley; the Center for Circuit and System Solutions at Carnegie Mellon University; the Interconnect Center at the Georgia Institute of Technology; the Material and Devices Center at the Massachusetts Institute of Technology; and the Center on Functional Engineered Nano Architectonics at the University of California, Los Angeles.
This year's DARPA Electronics Symposium, with attendance by invitation only, was an opportunity to look into the technical ideas and concepts that will lead to future high-impact MTO initiatives in integrated electronics. The majority of the presentations and discussions related to new, unpublished ideas and innovations. DARPA is a relatively flat organization with front-line program managers who report to the MTO director, who in turn reports to the DARPA director. The program managers are the primary interface to the technical community; they seek out innovative ideas and use them as the basis for new DARPA initiatives. The MTO program managers who predominantly (though not exclusively) interface with EDA-related activities are Robert Reuss and Daniel Radack. Both have graciously made themselves available to receive or discuss any ideas the EDA community members have to address the mounting challenges in design, verification, and test.
The symposium was an intensive three-day affair with unclassified sessions ranging from nanotechnology, unconventional electronics, nonsilicon electronics, and heterogeneous integration, to silicon platforms, design, and design automation challenges. In his opening remarks, John Zolper, MTO director, outlined MTO's vision of enabling systems with evolving capabilities—a vision that requires a shift from static component performance to a new generation focused on reconfigurable systems, adaptive components, and, eventually, intelligent components. Whereas the reconfigurable systems and components consist of a predefined deterministic set of operating parameters, an increasing level of autonomy with the ability to reason and learn with time characterizes adaptable and intelligent systems. Underlying these capabilities are the advances in sensing, processing, actuation, and power driven by advances in microelectronics. Examples of reconfigurable microsystems exist in intelligent RF front ends; microwave digital synthesizers; digitally controlled phase, amplitude, frequency modulation schemes; and tunable pixels. The eventual goal is to build a new class of autonomous systems that sport human-like sensor depth and capabilities to ensure persistent engagements, and explore the extreme limits of power and volume. The current programs focus on extending performance through conventional and unconventional means, by pursuing innovations in progression from new materials to new devices to new circuits and systems. These novelties are necessary to overcome challenges related to scaling and density in microelectronics, including the reduction of high defect rates, alternatives to lithography-based manufacturing, interfaces to hybrid technologies, and using EDA and reconfigurability to offset mounting design challenges that arise from new materials, devices, or even circuit types.
The participants discussed many emerging concepts and speculated on how various technologies might evolve. The important concepts relevant to our domain included using solution processing that seeks to build low-cost flexible circuits through direct digital printing technology using nanoparticles. End of scaling (EOS) in CMOS devices and circuits occupied a significant portion of the discussions. The presentations included discussions of EOS impacts on physical design (regularized designs without the use of subresolution assist features, canonical shapes, or sublithography patterning using self-assembly), electrical scaling (subthreshold electronics) and novel circuit structures, including digitally dominated analog circuits. The takeaway messages were as follows:

    • Although device-level scaling knobs (such as gate length, gate oxide, and mobility) might be maxed out, there exist several unexploited opportunities in scaling (for example, through sublithographic patterning) that can continue to yield the scaling benefits.

    • In the space between near-term device novelties such as FinFET, transport enhanced devices, and 3D integration versus far-end nanoelectronics, there is a significant space of new interface materials and device engineering. Exploiting opportunities in these areas could enable a new generation of subthreshold electronics, capable of pushing energy dissipation per function to theoretical limits that are about 1,000 times lower than that of the current technology generation, operating at the tens of millivolts.

    • The longer-term outlook will focus on transitioning to well-engineered and novel devices that could be part of all silicon platforms containing electronics, photonics, and sensors.

DARPA's MTO continues to drive innovations in miniaturization, function, power efficiency, SoCs, and newer circuit fabrics. It targets many of these material and component advances toward systems capabilities for adaptability and intelligence. There is a deep appreciation for the fact that such system advances absolutely require advances in models, methods, and tools to conceptualize, implement, and validate such systems. EDA is thus a critical ingredient to the task. CEDA welcomes your participation in building the vision for DARPA-led technical initiatives in the area. Please contact Louis Scheffer (lou@cadence.com) or Rajesh Gupta (rgupta@ucsd.edu) for more information.
CEDA Distinguished Speaker Series
Andreas Kuehlmann and Chuck Shaw, Cadence
CEDA is initiating a Distinguished Speaker Series. Each event will feature the winners of the best-paper awards from our premier forums (DAC, ICCAD, and IEEE Transactions on CAD). CEDA will invite the authors of these papers to give an in-depth presentation of their work, going beyond the published paper and conference talk. Each talk will take place before a live audience of experts, and discussions will follow the presentation. CEDA will videotape these events and post them on the CEDA Web site.
The first event will take place this spring in Silicon Valley, California. Zhenhai Zhu will discuss his William J. McCalla ICCAD 2005 best paper, "Fast Stochastic Integral Equation Solver." The second event will take place in July at DAC in San Francisco, in a session high-lighting CEDA's first year of activities.
2006 CANDE workshop to be held in Whistler, BC
CANDE, short for Computer-Aided Network Design (from the days when a "network" was another word for a "circuit") is the oldest continuing workshop in EDA, having started in 1972. The CANDE workshop was born out of an invitational group sponsored by Don Pederson of the University of California, Berkeley, as a means to create communication lines between designers and university researchers before the dawn of the EDA industry. CANDE is a technical committee of the IEEE Circuits and Systems Society and IEEE CEDA. CANDE cosponsors DAC and ICCAD. This year's annual CANDE workshop will be in Whistler, BC, from 21 to 23 September. Key items on the agenda include the following:

    • new cycles that could destroy the EDA industry,

    • the shift of EDA toward the "edges,"

    • the next open wave—open hardware?,

    • patent process opening and how it affects EDA, and

    • five disruptive technologies in the next five years.

To participate, visit http://www.cande.net or contactCANDE Publicity Chair Sylvia Chanak, syl@cadence.com.
Upcoming CEDA-sponsored events
Contact Dick Smith, vice president of conferences, dsmith@topher.net.

    • CODES+ISSS; http://www.esweek.org

    • DAC; http://www.dac.com

    • DATE; http://www.date-conference.com

    • FMCAD; http://www.fmcad.org

    • ICCAD; http://www.iccad.com

    • MEMOCODE; http://memocode.irisa.fr

    • MPSoC; http://tima.imag.fr/mpsoc

    • PATMOS; http://www.patmos-conf.org

    • VLSI-SOC; http://tima.imag.fr/conferences/VLSI-SoC06

    • Nano-Net; http://www.nanonets.org

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