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Issue No.02 - March/April (2006 vol.23)
pp: 128-136
Kaushik Roy , Purdue University
T.M. Mak , Intel
Kwang-Ting (Tim) Cheng , Universityy of California, Santa Barbara
ABSTRACT
Editor's note: Test technology faces new challenges as faults with increasingly complex behavior become predominant. Design approaches aimed at fixing some of the undesirable effects of nanometric technologies could jeopardize current test approaches. This article describes possible solutions to many of these challenges, including statistical timing and delay test, IDDQ test under exponentially increasing leakage, and power or thermal management architectures. --Michael Nicolaidis, iRoC Technologies
INDEX TERMS
deep-submicron test, nanometer technologies, statistical timing, delay test
CITATION
Kaushik Roy, T.M. Mak, Kwang-Ting (Tim) Cheng, "Test Consideration for Nanometer-Scale CMOS Circuits", IEEE Design & Test of Computers, vol.23, no. 2, pp. 128-136, March/April 2006, doi:10.1109/MDT.2006.52
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