CSDL - IEEE Design and Test of Computers

Design&Test
2005
Issue No. 6 - November/December

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IEEE Design & Test of Computers

November/December 2005 (vol. 22 no. 6)

ISSN: 0740-7475

Table of Contents

Demystifying 3D ICs: The Pros and Cons of Going Vertical (Abstract)

W. Rhett Davis, North Carolina State University

John Wilson, North Carolina State University

Stephen Mick, North Carolina State University

Jian Xu, North Carolina State University

Hao Hua, North Carolina State University

Christopher Mineo, North Carolina State University

Ambarish M. Sule, North Carolina State University

Michael Steer, North Carolina State University

Paul D. Franzon, North Carolina State University

pp. 498-510

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3D Chip Stack Technology Using Through-Chip Interconnects (Abstract)

Peter Benkart, Infineon Technologies and University of Ulm

Alexander Kaiser, University of Ulm

Andreas Munding, University of Ulm

Markus Bschorr, University of Ulm

Hans-Joerg Pfleiderer, University of Ulm

Erhard Kohn, University of Ulm

Arne Heittmann, Infineon Technologies

Holger Huebner, Infineon Technologies

Ulrich Ramacher, Infineon Technologies

pp. 512-518

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Predicting the Performance of a 3D Processor-Memory Chip Stack (Abstract)

Philip Jacob, Rensselaer Polytechnic Institute

Okan Erdogan, Rensselaer Polytechnic Institute

Aamir Zia, Rensselaer Polytechnic Institute

Paul M. Belemjian, Rensselaer Polytechnic Institute

Russell P. Kraft, Rensselaer Polytechnic Institute

John F. McDonald, Rensselaer Polytechnic Institute

pp. 540-547

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