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Issue No.06 - November/December (2005 vol.22)
pp: 604-615
Published by the IEEE Computer Society
This index includes all items appearing in this periodical during 2005 that are considered to have archival value. (The item title is listed only under the primary author entry in the author index.)

Author Index

A

Ababei, C., et al.,"Placement and routing in 3D integrated circuits"; Nov.-Dec. 05, pp. 520-531.

Abercrombie, D.,see Jahangiri, J., May-June 05, pp. 224-231.

Ahmadinia, A.,see Bobda, C., Sept.-Oct. 05, pp. 443-451.

Amirtharajah, R., see Thaker, D.D., July-Aug. 05, pp. 298-305.

B

Bahar, R.I., et al.,"Special section on advanced technologies and reliable design for nanotechnology systems"; July-Aug. 05, pp. 295-297.

Bai, X.,see Zhao, C., July-Aug. 05, pp. 362-375.

Baik D.H.,see Jeng-Liang Tsai, May-June 05, pp. 214-222.

Baumann, R."Soft errors in advanced computer systems"; May-June 05, pp. 258-266.

Bazargan, K.,see Ababei, C., Nov.-Dec. 05, pp. 520-531.

Becker, J., and A. Thomas, "Scalable processor instruction set extension"; Mar.–Apr. 05, pp. 136-148.

Belemjian, P.,see Jacob, P., Nov.-Dec. 05, pp. 540-547.

Benkart, P.,et al.,"3D chip stack technology using through chip interconnects"; Nov.-Dec. 05, pp. 512-518.

Berman, V.,"Is it time to reexamine patent policy for standards?"; Jan.-Feb. 05, pp. 71-73.

Berman, V.,"Sharing standards work with Japan [Standards]"; Mar.–Apr. 05, pp. 182-183.

Berman, V.,"IEEE P1647 and P1800: two approaches to standardization and language design"; May-June 05, pp. 283-285.

Berman, V.,"An update on IEEE P1647: The e system verification language"; Sept.-Oct. 05, pp. 484-486.

Blaauw, D.,see Rao, R.R., July-Aug. 05, pp. 376-385.

Bobda, C., and A. Ahmadinia, "Dynamic interconnection of reconfigurable modules on reconfigurable devices"; Sept.-Oct. 05, pp. 443-451.

Brodersen, R.W., see Chang, C., Mar.–Apr. 05, pp. 114-125.

Bschorr, M.,see Benkart, P., Nov.-Dec. 05, pp. 512-518.

Burtscher, M.,see Liu, C.C., Nov.-Dec. 05, pp. 556-564.

C

Carballo, J.-A., and Y. Zorian, "Guest editors' introduction: DFM drives changes in design flow [special section intro.]"; May-June 05, pp. 200-205.

Catthoor, F.,see Resano, J., Sept.-Oct. 05, pp. 452-461.

Chakradhar, S.T., see Lv, T., Jan.-Feb. 05, pp. 18-26.

Chang, C., J. Wawrzynek, and R.W. Brodersen. BEE2: a high-end reconfigurable computing system"; Mar.–Apr. 05, pp. 114-125.

Chang, M.L., and S. Hauck. "Precis: a usercentric word-length optimization tool"; July-Aug. 05, pp. 349-361.

Chen H., M.F. Jacome, and G. de Veciana. "A reconfiguration-based defect-tolerant design paradigm for nanotechnologies"; July-Aug. 05, pp. 316-326.

C.C-.P. Chenm, see J.-L. Tsai, May-June 05, pp. 214-222.

Chong, F.T., see Thaker, D.D., July-Aug. 05, pp. 298-305.

Chou, P.H., see Park, C., Mar.–Apr. 05, pp. 150-159.

Chuang, I.L., see Thaker, D.D., July-Aug. 05, pp. 298-305.

Chung L.L., see Ming S. W., Mar.–Apr. 05, pp. 160-169.

Cohen, E.,see Yeric, G., May-June 05, pp. 232-239.

D

Davidson, S. "BIST the hard way [review of "A Designer's Guide to Built-In Self-Test" (Stroud, C.E."; 2002)]"; July-Aug. 05, pp. 386-387.

Davis, K.,see Yeric, G., May-June 05, pp. 232-239.

Davis, W.R., et al.,"Demystifying 3D ICs: The pros and cons of going vertical"; Nov.-Dec. 05, pp. 498-510.

DeHon, A., and H. Naeimi, "Seven strategies for tolerating highly defective fabrication"; July-Aug. 05, pp. 306-315.

Delaney, B., N. Jayant, and T. Simunic, "Energy-aware distributed speech recognition for wireless mobile devices"; Jan.-Feb. 05, pp. 39-49.

de Lima Kastensmidt, F.G., see Neuberger, G., Jan.-Feb. 05, pp. 50-58.

de Mello, B.A., et al.,"Tangram: Virtual integration of IP components in a distributed cosimulation environment"; Sept.-Oct. 05, pp. 462-471.

De Micheli, G., see Ivanov, A., Sept.-Oct. 05, pp. 399-403.

De Micheli, G., see Pande, P.P., Sept.-Oct. 05, pp. 404-413.

de Veciana, G., see C. H., July-Aug. 05, pp. 316-326.

Devgan, A.,see Rao, R.R., July-Aug. 05, pp. 376-385.

Dey, S.,see Zhao, C., July-Aug. 05, pp. 362-375.

Dielissen, J.,see Goosens, K., Sept.-Oct. 05, pp. 414-421.

Dong H. B., see Jeng-Liang Tsai, May-June 05, pp. 214-222.

E

Erdogan, O.,see Jacob, P., Nov.-Dec. 05, pp. 540-547.

F

Feng Y., see Ababei, C., Nov.-Dec. 05, pp. 520-531.

Fortes, J.A.B., see Jie Han, July-Aug. 05, pp. 328-339.

Franzon, P.,see Davis, W.R., Nov.-Dec. 05, pp. 498-510.

G

Ganusov, I.,see Liu, C.C., Nov.-Dec. 05, pp. 556-564.

Gao, J.,see Jie H., July-Aug. 05, pp. 328-339.

Garcia, J.,see Yeric, G., May-June 05, pp. 232-239.

Goosens, K., J. Dielissen, and A. Radulescu. "Aetheral network on chip: Concepts, architectures, and implementations"; Sept.-Oct. 05, pp. 414-421.

Goplen, B.,see Ababei, C., Nov.-Dec. 05, pp. 520-531.

Grecu, C.,see Pande, P.P., Sept.-Oct. 05, pp. 404-413.

Green, G.,see Yeric, G., May-June 05, pp. 232-239.

Gutmann, R.J., see Yujuan Z., Nov.-Dec. 05, pp. 548-555.

H

Hamling, D.T. "Test solution selection using multiple-objective decision models and analyses"; Mar.–Apr. 05, pp. 126-134.

Han Jie, see Jie H., July-Aug. 05, pp. 328-339.

Hao H., see Davis, W.R., Nov.-Dec. 05, pp. 498-510.

Hauck, S.,see Chang, M.L., July-Aug. 05, pp. 349-361.

He C., see Chen H., July-Aug. 05, pp. 316-326.

Heittmann, A.,see Benkart, P., Nov.-Dec. 05, pp. 512-518.

Henkel, J.,see Lv, T., Jan.-Feb. 05, pp. 18-26.

Hsiao, M.S., see Xiao L., Nov.-Dec. 05, pp. 576-584.

Hua Hao, see Davis, W.R., Nov.-Dec. 05, pp. 498-510.

Huebner, H.,see Benkart, P., Nov.-Dec. 05, pp. 512-518.

Hyun B. D., see Jeng-Liang T., May-June 05, pp. 214-222.

I

Ienne, P.,see Vuletid, M., Mar.–Apr. 05, pp. 102-113.

Impens, F.,see Thaker, D.D., July-Aug. 05, pp. 298-305.

Ivanov, A., and G. De Micheli. "Guest editors' introduction: The Network-on-Chip paradigm in practice and research"; Sept.-Oct. 05, pp. 399-403.

Ivanov, A.,see Pande, P.P., Sept.-Oct. 05, pp. 404-413.

J

Jacob, P.,et al.,"Predicting 3D processor memory chip stack performance"; Nov.-Dec. 05, pp. 540-547.

Jacome, M.F., see Chen H., July-Aug. 05, pp. 316-326.

Jahangiri, J., and D. Abercrombie. "Value-added defect testing techniques"; May-June 05, pp. 224-231.

Jayant, N.,see Delaney, B., Jan.-Feb. 05, pp. 39-49.

Jeng-Liang T., et al.,"Yield-driven, false-path-aware clock skew scheduling"; May-June 05, pp. 214-222.

Jiang X., see Lv, T., Jan.-Feb. 05, pp. 18-26.

Jonker, P.,see Jie H., July-Aug. 05, pp. 328-339.

K

Kaiser, A.,see Benkart, P., Nov.-Dec. 05, pp. 512-518.

Kangmin Lee, see Se-Joong L., Sept.-Oct. 05, pp. 422-433.

Katoch, A.,see Rossi, D., Jan.-Feb. 05, pp. 59-70.

Katoch, A.,see Rossi, D., July-Aug. 05, pp. 340-348.

Kohn, E.,see Benkart, P., Nov.-Dec. 05, pp. 512-518.

Kraft, R.P., see Jacob, P., Nov.-Dec. 05, pp. 540-547.

Kyu L. S., see Sung Kyu Lim, Nov.-Dec. 05, pp. 532-539.

L

Lambrechts, A.,see Mei, B., Mar.–Apr. 05, pp. 90-101.

La Rosa, A., L. Lavagno, and C. Passerone. "Software development for high-performance, reconfigurable, embedded multimedia systems"; Jan.-Feb. 05, pp. 28-38.

Lauwereins, R.,see Mei, B., Mar.–Apr. 05, pp. 90-101.

Lavagno, L.,see La Rosa, A., Jan.-Feb. 05, pp. 28-38.

Lee C. L., see Ming S. W., Mar.–Apr. 05, pp. 160-169.

Lee Kangmin, see S.-J. Lee, Sept.-Oct. 05, pp. 422-433.

Lee S.-J., see S.-J. Lee, Sept.-Oct. 05, pp. 422-433.

Len L. C., see Ming S. W., Mar.–Apr. 05, pp. 160-169.

Lim S. K., see Sung K. L., Nov.-Dec. 05, pp. 532-539.

Liu, C.C., I. et al.,"Bridging the processor-memory performance gap with 3-D IC technology"; Nov.-Dec. 05, pp. 556-564.

Liu, J.,see Park, C., Mar.–Apr. 05, pp. 150-159.

Liu X., see L. Xiao, Nov.-Dec. 05, pp. 576-584.

Lombardi, F.,see Bahar, R.I., July-Aug. 05, pp. 295-297.

Lu J.-Q., see Yujuan Z., Nov.-Dec. 05, pp. 548-555.

Lumetta, S.S., see Mitra, S., Nov.-Dec. 05, pp. 566-574.

Lv, T.,et al.,"A methodology for architectural design of multimedia multiprocessor SoCs"; Jan.-Feb. 05, pp. 18-26.

Lysaght, P., and P.A. Subrahmanyam. "Guest editors' introduction: Advances in configurable computing [special section intro.]"; Mar.–Apr. 05, pp. 85-89.

M

Madge, R. "New test paradigms for yield and manufacturability"; May-June 05, pp. 240-246.

Martin, G. "The network is the chip [review of "Interconnect-Centric Design for Advanced DoC and NoC" (Nurmi, J. et al., eds."; 2004)]"; Mar.–Apr. 05, pp. 184-185.

Martin, G. "Verification by the pound [review of "Comprehensive Functional Verification" (Goss, J.C. and Roesner, W."; 05)]"; Sept.-Oct. 05, pp. 478-479.

Maunder, C. "TTTC recognizes JTAG leader's lifetime contribution [Conference Reports]"; Jan.-Feb. 05, pp. 76.

McDonald, J.F., see Jacob, P., Nov.-Dec. 05, pp. 540-547.

Mei, B.,et al.,"Architecture exploration for a reconfigurable architecture template"; Mar.–Apr. 05, pp. 90-101.

Metra, C.,see Rossi, D., Jan.-Feb. 05, pp. 59-70.

Metra, C.,see Rossi, D., July-Aug. 05, pp. 340-348.

Mick, S.,see Davis, W.R., Nov.-Dec. 05, pp. 498-510.

Mignolet, J.-Y., see Mei, B., Mar.–Apr. 05, pp. 90-101.

Mineo, C.,see Davis, W.R., Nov.-Dec. 05, pp. 498-510.

Ming S. W., and Chung Len Lee. "Using a periodic square wave test signal to detect crosstalk faults"; Mar.–Apr. 05, pp. 160-169.

Mitra, S.,et al.,"X-tolerant test response compaction"; Nov.-Dec. 05, pp. 566-574.

Mitzenmacher, M., see Mitra, S., Nov.-Dec. 05, pp. 566-574.

Mneimneh, M.N., and K.A. Sakallah. "Principles of sequential-equivalence verification"; May-June 05, pp. 248-257.

Mogal, H.,see Ababei, C., Nov.-Dec. 05, pp. 520-531.

Mozos, D.,see Resano, J., Sept.-Oct. 05, pp. 452-461.

Munding, A.,see Benkart, P., Nov.-Dec. 05, pp. 512-518.

N

Naeimi, H.,see DeHon, A., July-Aug. 05, pp. 306-315.

Neuberger, G., F.G. de Lima Kastensmidt, and R. Reis. "An automatic technique for optimizing Reed-Solomon codes to improve fault tolerance in memories"; Jan.-Feb. 05, pp. 50-58.

Nieuwland, A.K., see Rossi, D., Jan.-Feb. 05, pp. 59-70.

Nieuwland, A.K., see Rossi, D., July-Aug. 05, pp. 340-348.

O

Ozer, I.B., see Lv, T., Jan.-Feb. 05, pp. 18-26.

P

Pande, P.P., et al.,"Design, synthesis, and test of networks on chips"; Sept.-Oct. 05, pp. 404-413.

Park, C., J. Liu, and P.H. Chou, "B#: a battery emulator and power-profiling instrument"; Mar.–Apr. 05, pp. 150-159.

Passerone, C.,see La Rosa, A., Jan.-Feb. 05, pp. 28-38.

Patil, N.,see Mitra, S., Nov.-Dec. 05, pp. 566-574.

Pfleiderer, H.-J., see Benkart, P., Nov.-Dec. 05, pp. 512-518.

Pozzi, L.,see Vuletid, M., Mar.–Apr. 05, pp. 102-113.

Q

Qi Y., see Jie H., July-Aug. 05, pp. 328-339.

R

Radulescu, A.,see Goosens, K., Sept.-Oct. 05, pp. 414-421.

Ramacher, U.,see Benkart, P., Nov.-Dec. 05, pp. 512-518.

Rao, R.R.,et al.,"Modeling and analysis of parametric yield under power and performance constraints"; July-Aug. 05, pp. 376-385.

Reis, R.,see Neuberger, G., Jan.-Feb. 05, pp. 50-58.

Resano, J.,et al.,"A reconfiguration manager for dynamically reconfigurable hardware"; Sept.-Oct. 05, pp. 452-461.

Rodgers, T. "The truth about outsourcing"; Jan.-Feb. 05, pp. 12-13.

Rose, K.,see Yujuan Zeng, Nov.-Dec. 05, pp. 548-555.

Rossi, D.,et al.,"Exploiting ECC redundancy to minimize crosstalk impact"; Jan.-Feb. 05, pp. 59-70.

Rossi, D.,et al.,"New ECC for crosstalk impact minimization"; July-Aug. 05, pp. 340-348.

S

Sabade, S.S., and D.M.H. Walker. "IC outlier identification using multiple test metrics"; Nov.-Dec. 05, pp. 586-595.

Sakallah, K.A., see Mneimneh, M.N., May-June 05, pp. 248-257.

Saleh, R.,see Pande, P.P., Sept.-Oct. 05, pp. 404-413.

Salem, E.,see Yeric, G., May-June 05, pp. 232-239.

Saluja, K.K., see Jeng-Liang T., May-June 05, pp. 214-222.

Sangiovanni-Vincentelli, A. "The importance of innovation in the economy of advanced countries"; Jan.-Feb. 05, pp. 14-16.

Sapatnekar, S. "The Electronic Design Automation Handbook (Jansen, D."; 2003) [book review]"; Jan.-Feb. 05, pp. 74-75.

Sapatnekar, S. "Empowering the designer [review of "Low Voltage, Low Power VLSI Subsystems" (Kiat-Seng, Y. and Roy, K."; 2004)]"; May-June 05, pp. 280-281.

Sapatnekar, S.S., see Ababei, C., Nov.-Dec. 05, pp. 520-531.

Se-Joong Lee, K. Lee, and H.-J. Yoo. "Analysis and implementation of practical, cost-effective networks on chips"; Sept.-Oct. 05, pp. 422-433.

Shae, W. M., see Ming S. W.., Mar.–Apr. 05, pp. 160-169.

Shukla, S.K., see Bahar, R.I., July-Aug. 05, pp. 295-297.

Simunic, T.,see Delaney, B., Jan.-Feb. 05, pp. 39-49.

Souza, U.R.F., see de Mello, B.A., Sept.-Oct. 05, pp. 462-471.

Sperb, J.K., see de Mello, B.A., Sept.-Oct. 05, pp. 462-471.

Steer, M.,see Davis, W.R., Nov.-Dec. 05, pp. 498-510.

Subrahmanyam, P.A., see Lysaght, P., Mar.–Apr. 05, pp. 85-89.

Sule, A.,see Davis, W.R., Nov.-Dec. 05, pp. 498-510.

Sung K. L. "Physical design for 3D system-on-package: Challenges and opportunities"; Nov.-Dec. 05, pp. 532-539.

Sylvester, D.,see Rao, R.R., July-Aug. 05, pp. 376-385.

T

Tahoori, M.B., see Bahar, R.I., July-Aug. 05, pp. 295-297.

Thaker, D.D., et al.,"Recursive TMR: scaling fault tolerance in the nanoscale era"; July-Aug. 05, pp. 298-305.

Thomas, A.,see Becker, J., Mar.–Apr. 05, pp. 136-148.

Tianpei Z., see Ababei, C., Nov.-Dec. 05, pp. 520-531.

Tiwari, S.,see Liu, C.C., Nov.-Dec. 05, pp. 556-564.

Tsai J.-L., see Tsai J.-L., May-June 05, pp. 214-222.

U

Unger, S.H. "Is engineering a viable profession in the US?"; Jan.-Feb. 05, pp. 10-11.

V

Verkest, D.,see Mei, B., Mar.–Apr. 05, pp. 90-101.

Verkest, D.,see Resano, J., Sept.-Oct. 05, pp. 452-461.

Vuletid, M., L. Pozzi, and P. Ienne. "Seamless hardware-software integration in reconfigurable computing systems"; Mar.–Apr. 05, pp. 102-113.

W

Wagner, F.R., see de Mello, B.A., Sept.-Oct. 05, pp. 462-471.

Wagner, K. "Keeping current with silicon and systems technology in the mid-90s"; Jan.-Feb. 05, pp. 7-9.

Wagner, K. "Driving the $5 billion innovation engine at Intel [Interview]"; Mar.–Apr. 05, pp. 170-180.

Walker, D.M.H., see Sabade, S.S., Nov.-Dec. 05, pp. 586-595.

Wawrzynek, J.,see Chang, C., Mar.–Apr. 05, pp. 114-125.

Wilson, J.,see Davis, W.R., Nov.-Dec. 05, pp. 498-510.

Wolf, W.,see Lv, T., Jan.-Feb. 05, pp. 18-26.

Wong, A.K. "Some thoughts on the IC design-manufacture interface"; May-June 05, pp. 206-213.

Wu M. S., see Wu M. S., Mar.–Apr. 05, pp. 160-169.

X

Xiao L., and M.S. Hsiao. "Novel transition fault ATPG to reduce yield loss"; Nov.-Dec. 05, pp. 576-584.

Xu Jian, see Davis, W.R., Nov.-Dec. 05, pp. 498-510.

Xu Jiang, see Lv, T., Jan.-Feb. 05, pp. 18-26.

Y

Yan Feng, see Ababei, C., Nov.-Dec. 05, pp. 520-531.

Yan Q., see Jie H., July-Aug. 05, pp. 328-339.

Yeric, G.,et al.,"Infrastructure for successful BEOL yield ramp, transfer to manufacturing, and DFM characterization at 65 nm and below"; May-June 05, pp. 232-239.

Yoo H.-J., see Lee S.-J., Sept.-Oct. 05, pp. 422-433.

Yujuan Z., J.-Q. Lu, K. Rose, and R.J. Gutmann. "First-order performance prediction of cache memory with wafer-level 3D integration"; Nov.-Dec. 05, pp. 548-555.

Z

Zeng Y., see Yujuan Z., Nov.-Dec. 05, pp. 548-555.

Zhang T., see Ababei, C., Nov.-Dec. 05, pp. 520-531.

Zhao, C., S. Dey, and X. Bai. "Soft-spot analysis: targeting compound noise effects in nanometer circuits"; July-Aug. 05, pp. 362-375.

Zia, A.,see Jacob, P., Nov.-Dec. 05, pp. 540-547.

Zorian, Y.,see Carballo, J.-A., May-June 05, pp. 200-205.

Zorian, Y.,"Inventions: A result of risk-taking, diversity, and holistic thinking"; Sept.-Oct. 05, pp. 472-477.

Subject Index

Application specific integrated circuits

parametric yield under power and perform. constraints, modeling and anal., Rao, R.R., July-Aug. 05, pp. 376-385.

placement and routing in 3D integrated circuits. Ababei, C., Nov.-Dec. 05, pp. 520-531.

Application specific integrated circuits,
see , System-on-chip
Automata

seq.-equivalence verification, principles, Mneimneh, M.N., May-June 05, pp. 248-257.

Automatic test equipment

test soln. selection, multiple-objective decision models and anals., Hamling, D.T., Mar.–Apr. 05, pp. 126-134.

Automatic testing

test soln. selection, multiple-objective decision models and anals., Haling, D.T., Mar.-Apr. 05, pp. 126-134.

Automatic testing,
see Automatic test pattern generation
Automatic test pattern generation

novel transition fault ATPG to reduce yield loss, Xiao Liu, Nov.-Dec. 05, pp. 576-584.

Awards

IEEE Computer Society's Test Technology Technical Council presents Lifetime Contribution Medal to Rod Tulloss, Maunder, C., Jan.-Feb. 05, pp. 76.

Batteries

B#, batt. emulator and power-profiling instrum., Park, C., Mar.–Apr. 05, pp. 150-159.

Bifurcation

nanoelectronics, hardware-redundant, fault-tolerant logic, Jie Han, July-Aug. 05, pp. 328-339.

Book reviews

A Designer's Guide to Built-In Self-Test (Stroud, C.E.; 2002), Davidson, S., July-Aug. 05, pp. 386-387.

Comprehensive Functional Verification (Goss, J.C. and Roesner, W.; 05), Martin, G., Sept.-Oct. 05, pp. 478-479.

Interconnect-Centric Design for Advanced DoC and NoC (Nurmi, J. et al., eds.; 2004), Martin, G., Mar.–Apr. 05, pp. 184-185.

Low Voltage, Low Power VLSI Subsystems (Kiat-Seng Yeo and Roy, K.; 2004), Sapatnekar, S., May-June 05, pp. 280-281.

The Electronic Design Automation Handbook (Jansen, D.; 2003), Sapatnekar, S., Jan.-Feb. 05, pp. 74-75.

Buffer storage,
see Cache storage
Built-in self test

book review; A Designer's Guide to Built-In Self-Test (Stroud, C.E.; 2002), Davidson, S., July-Aug. 05, pp. 386-387.

Cache memories

scalable processor instruction set extension. Becker, J., Mar.–Apr. 05, pp. 136-148.

Cache storage

first-order performance prediction of cache memory with wafer-level 3D integration, Yujuan Z., Nov.-Dec. 05, pp. 548-555.

CAD,
see Electronic design automation
Cameras,
see Video cameras
Circuit noise,
see Integrated circuit noise
Circuit reliability,
see Integrated circuit reliability
Circuit testing,
see Integrated circuit testing
Client-server systems

wireless mobile devices, energy-aware distrib. speech recogn. Delaney, B., Jan.-Feb. 05, pp. 39-49.

Clocks

yield-driven, false-path-aware clock skew sched. Tsai J.-L., May-June 05, pp. 214-222.

CMOS integrated circuits

yield and manufacturability, test paradigms, Madge, R., May-June 05, pp. 240-246.

Code division multiaccess

innovation, future depends. May-June 05, pp. 268-279.

Codes,
see Dual codes, Hamming codes, Reed-Solomon codes
Commerce,
see Investment
Communication system traffic

wireless mobile devices, energy-aware distrib. speech recogn.. Delaney, B., Jan.-Feb. 05, pp. 39-49.

Compaction

X-tolerant test response compaction, Mitra, S., Nov.-Dec. 05, pp. 566-574.

Computational geometry

IC design-manufacture interface, thoughts, Wong, A.K., May-June 05, pp. 206-213.

Computer applications,
see Multimedia systems
Computer architecture,

Aetheral NoC, concepts, archit. and implement., Goosens, K., Sept.-Oct. 05, pp. 414-421.

crosstalk impact minimization, ECC, Rossi, D., July-Aug. 05, pp. 340-348.

dynamic interconnection of reconfig. modules on reconfig. devices, Bobda, C., Sept.-Oct. 05, pp. 443-451.

precis, usercentric word-length optim. tool, Chang, M.L., July-Aug. 05, pp. 349-361.

reconfig. manager for dynamically reconfig. hardware, Resano, J., Sept.-Oct. 05, pp. 452-461.

Computer architecture,
see Memory architecture, Reconfigurable architectures, Reduced instruction set computing
Computer fault tolerance

minimize crosstalk impact, exploiting ECC redundancy, Rossi, D., Jan.-Feb. 05, pp. 59-70.

optimizing RS codes, improve fault tolerance, memories, automatic tech., Neuberger, G., Jan.-Feb. 05, pp. 50-58.

Computer graphics,
see Virtual reality
Computer instructions

high-perform., reconfigurable, embedded multimedia systs., software develop.. La Rosa, A., Jan.-Feb. 05, pp. 28-38.

reconfigurable archit. template, archit. exploration, Mei, B., Mar.–Apr. 05, pp. 90-101.

scalable processor instruction set extension, Becker, J., Mar.–Apr. 05, pp. 136-148.

Computer interfaces,
see Network interfaces
Computerized instrumentation,
see Automatic test equipment
Computer networks,
see Internetworking
Computer power supplies

B#, batt. emulator and power-profiling instrum., Park, C., Mar.–Apr. 05, pp. 150-159.

Configuration management

configurable computing, fabric and systems (special section), Mar.–Apr. 05, pp. 85-125.

configurable computing, fabric and systems (special section intro.), Lysaght, P., Mar.–Apr. 05, pp. 85-89.

Costing

analysis and implement. of practical, cost-effective NoCs. Lee, S.-J., Sept.-Oct. 05, pp. 422-433.

Crosstalk

impact minimization, ECC. Rossi, D., July-Aug. 05, pp. 340-348.

minimize crosstalk impact, exploiting ECC redundancy, Rossi, D., Jan.-Feb. 05, pp. 59-70.

periodic sq. wave test sig., detect crosstalk faults, S. W., Ming, Mar.–Apr. 05, pp. 160-169.

Data buses

crosstalk impact minimization, ECC, Rossi, D., July-Aug. 05, pp. 340-348.

minimize crosstalk impact, exploiting ECC redundancy, Rossi, D., Jan.-Feb. 05, pp. 59-70.

Delay effects

minimize crosstalk impact, exploiting ECC redundancy, Rossi, D., Jan.-Feb. 05, pp. 59-70.

Design

book review; Interconnect-Centric Design for Advanced DoC and NoC (Nurmi, J. et al., eds.; 2004), Martin, G., Mar.–Apr. 05, pp. 184-185.

Design automation

IC design-manufacture interface, thoughts, Wong, A.K., May-June 05, pp. 206-213.

Design engineering,
see Design for testability
Design for testability

value-added defect testing techs., Jahangiri, J., May-June 05, pp. 224-231.

yield and manufacturability, test paradigms, Madge, R., May-June 05, pp. 240-246.

Design methodology

successful BEOL yield ramp, transfer, mfg., DFM charactn., 65 nm and below, infrastructure, Yeric, G., May-June 05, pp. 232-239.

value-added defect testing techs., Jahangiri, J., May-June 05, pp. 224-231.

yield and manufacturability, test paradigms, Madge, R., May-June 05, pp. 240-246.

yield-driven, false-path-aware clock skew sched.. Tsai, J.-L., May-June 05, pp. 214-222.

Digital arithmetic,
see Redundant number systems
Digital computers,
see Microcomputers
Digital integrated circuits,
see Integrated memory circuits
Digital signal processing chips

design, synthesis, and test of networks on chips, Pande, P.P., Sept.-Oct. 05, pp. 404-413.

networks on chips (special section), Sept.-Oct. 05, pp. 399-451.

networks on chips (special section intro.), Ivanov, A., Sept.-Oct. 05, pp. 399-403.

Digital signal processors

BEE2, high-end reconfigurable comput. syst., Chang, C., Mar.–Apr. 05, pp. 114-125.

Display instrumentation,
see Three-dimensional displays
Distributed processing

Tangram, virtual integration of IP components in a distributed cosimulation environ., de Mello, B.A., Sept.-Oct. 05, pp. 462-471.

Distributed processing,
see Client-server systems, Pipeline processing
DRAM chips

advanced computer systs., soft errors, Baumann, R., May-June 05, pp. 258-266.

bridging the processor-memory performance gap with 3-D IC technol., Liu, C.C., Nov.-Dec. 05, pp. 556-564.

Dual codes

minimize crosstalk impact, exploiting ECC redundancy, Rossi, D., Jan.-Feb. 05, pp. 59-70.

Education,
see Engineering education
Electric variables control,
see Voltage control
Electron device manufacture,
see Integrated circuit manufacture, Semiconductor device manufacture
Electronic design automation

book review; The Electronic Design Automation Handbook (Jansen, D.; 2003), Sapatnekar, S., Jan.-Feb. 05, pp. 74-75.

Electronic engineering,
see Low-power electronics
Electronic engineering computing,
see Electronic design automation, SPICE
Electronics industry

successful BEOL yield ramp, transfer, mfg., DFM charactn., 65 nm and below, infrastructure, Yeric, G., May-June 05, pp. 232-239.

Employment

innovation, economy of advanced countries, importance. Sangiovanni-Vincentelli, A., Jan.-Feb. 05, pp. 14-16.

Engineering

US, engng., viable profession. Unger, S.H., Jan.-Feb. 05, pp. 10-11.

Engineering,
see Engineering education
Engineering education

innovation, economy of advanced countries, importance, Sangiovanni-Vincentelli, A., Jan.-Feb. 05, pp. 14-16.

Engineering profession

innovation, economy of advanced countries, importance, Sangiovanni-Vincentelli, A., Jan.-Feb. 05, pp. 14-16.

US, engng., viable profession, Unger, S.H., Jan.-Feb. 05, pp. 10-11.

Error analysis

advanced computer systs., soft errors, Baumann, R., May-June 05, pp. 258-266.

Error correction

advanced computer systs., soft errors, Baumann, R., May-June 05, pp. 258-266.

Error correction coding

crosstalk impact minimization, ECC, Rossi, D., July-Aug. 05, pp. 340-348.

minimize crosstalk impact, exploiting ECC redundancy, Rossi, D., Jan.-Feb. 05, pp. 59-70.

optimizing RS codes, improve fault tolerance, memories, automatic tech., Neuberger, G., Jan.-Feb. 05, pp. 50-58.

Error detection coding

optimizing RS codes, improve fault tolerance, memories, automatic tech., Neuberger, G., Jan.-Feb. 05, pp. 50-58.

Failure analysis

keeping current, Si and systs. technol., mid-90s, Wagner, K., Jan.-Feb. 05, pp. 7-9.

Fault currents,
see Leakage currents
Fault diagnosis

advanced computer systs., soft errors, Baumann, R., May-June 05, pp. 258-266.

IC outlier identification using multiple test metrics, Sabade, S.S., Nov.-Dec. 05, pp. 586-595.

successful BEOL yield ramp, transfer, mfg., DFM charactn., 65 nm and below, infrastructure, Yeric, G., May-June 05, pp. 232-239.

value-added defect testing techs., Jahangiri, J., May-June 05, pp. 224-231.

Fault tolerance

advanced technologies and reliable design for nanotechnology systems (special section), July-Aug. 05, pp. 295-339.

advanced technologies and reliable design for nanotechnology systems (special section intro.), Bahar, R.I., July-Aug. 05, pp. 295-297.

Fault tolerance,
see Fault tolerant computing
Fault tolerant computing

X-tolerant test response compaction, Mitra, S., Nov.-Dec. 05, pp. 566-574.

Field programmable gate arrays

configurable computing, fabric and systems (special section), Mar.–Apr. 05, pp. 85-125.

configurable computing, fabric and systems (special section intro.), Lysaght, P., Mar.–Apr. 05, pp. 85-89.

high-perform., reconfigurable, embedded multimedia systs., software develop., La Rosa, A., Jan.-Feb. 05, pp. 28-38.

tolerating highly defective fab., 7 strategies, DeHon, A., July-Aug. 05, pp. 306-315.

Finance,
see Costing, Investment
Formal verification,
see Program verification
Functional programming

book review; Comprehensive Functional Verification (Goss, J.C. and Roesner, W.; 05), Martin, G., Sept.-Oct. 05, pp. 478-479.

Geometry,
see Computational geometry
Globalization

perspectives on outsourcing (special section), Jan.-Feb. 05, pp. 10-16.

Government policies,
see Research initiatives
Graphical user interfaces

B#, batt. emulator and power-profiling instrum., Park, C., Mar.–Apr. 05, pp. 150-159.

Hamming codes

minimize crosstalk impact, exploiting ECC redundancy, Rossi, D., Jan.-Feb. 05, pp. 59-70.

Hardware design languages

IEEE P1647 and P1800, Berman, V., May-June 05, pp. 283-285.

IEEE

keeping current in IEEE Design & Test Magazine, Si and systs. technol., mid-90s, Wagner, K., Jan.-Feb. 05, pp. 7-9.

IEEE standards

IEEE P1647, e system verification language, Berman, V., Sept.-Oct. 05, pp. 484-486.

P1647 and P1800, Berman, V., May-June 05, pp. 283-285.

reexamine patent policies for standards, Berman, V., Jan.-Feb. 05, pp. 71-73.

sharing standards work with Japan, Berman, V., Mar.–Apr. 05, pp. 182-183.

Image coding,
see Video coding
Industrial property,
see Patents
Industries,
see Electronics industry
Information theory,
see Prediction theory
Innovation management

driving the $5 billion innovation engine at Intel, Wagner, K., Mar.–Apr. 05, pp. 170-180.

Instruments,
see Clocks
Integrated circuit design

3D chip stack technology using through chip interconnects, Benkart, P., Nov.-Dec. 05, pp. 512-518.

book review; Interconnect-Centric Design for Advanced DoC and NoC (Nurmi, J. et al., eds.; 2004), Martin, G., Mar.–Apr. 05, pp. 184-185.

book review; Low Voltage, Low Power VLSI Subsystems (Kiat-Seng Yeo and Roy, K.; 2004), Sapatnekar, S., May-June 05, pp. 280-281.

demystifying 3D ICs, pros and cons of going vertical, Davis, W.R., Nov.-Dec. 05, pp. 498-510.

design-manufacture interface, thoughts, Wong, A.K., May-June 05, pp. 206-213.

IEEE P1647 and P1800. Berman, V., May-June 05, pp. 283-285.

keeping current, Si and systs. technol., mid-90s, Wagner, K., Jan.-Feb. 05, pp. 7-9.

parametric yield under power and perform. constraints, modeling and anal., Rao, R.R., July-Aug. 05, pp. 376-385.

physical design for 3D system-on-package, Lim, S. K., Nov.-Dec. 05, pp. 532-539.

yield-driven, false-path-aware clock skew sched., Tsai, J.-L., May-June 05, pp. 214-222.

Integrated circuit manufacture

design-manufacture interface, thoughts, Wong, A.K., May-June 05, pp. 206-213.

Integrated circuit noise

soft-spot anal., targeting cpd. noise effects, nanometer ccts., Zhao, C., July-Aug. 05, pp. 362-375.

Integrated circuit reliability

nanoelectronics, hardware-redundant, fault-tolerant logic, Han, J., July-Aug. 05, pp. 328-339.

nanoscale era, recursive TMR, scaling fault tolerance, Thaker, D.D., July-Aug. 05, pp. 298-305.

soft-spot anal., targeting cpd. noise effects, nanometer ccts., Zhao, C., July-Aug. 05, pp. 362-375.

Integrated circuits

book review; Comprehensive Functional Verification (Goss, J.C. and Roesner, W.; 05), Martin, G., Sept.-Oct. 05, pp. 478-479.

demystifying 3D ICs, pros and cons of going vertical, Davis, W.R., Nov.-Dec. 05, pp. 498-510.

IC outlier identification using multiple test metrics, Sabade, S.S., Nov.-Dec. 05, pp. 586-595.

placement and routing in 3D integrated circuits, Ababei, C., Nov.-Dec. 05, pp. 520-531.

predicting 3D processor memory chip stack performance, Jacob, P., Nov.-Dec. 05, pp. 540-547.

Integrated circuits,
see Monolithic integrated circuits
Integrated circuit testing

nanoelectronics, hardware-redundant, fault-tolerant logic, Han, J., July-Aug. 05, pp. 328-339.

nanoscale era, recursive TMR, scaling fault tolerance, Thaker, D.D., July-Aug. 05, pp. 298-305.

periodic sq. wave test sig., detect crosstalk faults, Wu, M. S., Mar.–Apr. 05, pp. 160-169.

soft-spot anal., targeting cpd. noise effects, nanometer ccts., Zhao, C., July-Aug. 05, pp. 362-375.

successful BEOL yield ramp, transfer, mfg., DFM charactn., 65 nm and below, infrastructure, Yeric, G., May-June 05, pp. 232-239.

value-added defect testing techs., Jahangiri, J., May-June 05, pp. 224-231.

yield and manufacturability, test paradigms, Madge, R., May-June 05, pp. 240-246.

Integrated memory circuits

bridging the processor-memory performance gap with 3-D IC technol., Liu, C.C., Nov.-Dec. 05, pp. 556-564.

Integrated memory circuits,
see DRAM chips, SRAM chips
Interactive systems,
see Virtual reality
Interference (signal),
see Crosstalk
International collaboration

sharing standards work with Japan, Berman, V., Mar.–Apr. 05, pp. 182-183.

Internetworking

dynamic interconnection of reconfig. modules on reconfig. devices, Bobda, C., Sept.-Oct. 05, pp. 443-451.

networks on chips (special section), Sept.-Oct. 05, pp. 399-451.

networks on chips (special section intro.), Ivanov, A., Sept.-Oct. 05, pp. 399-403.

Interviews

driving the $5 billion innovation engine at Intel, Wagner, K., Mar.–Apr. 05, pp. 170-180.

inventions, a result of risk-taking, diversity, and holistic thinking, Zorian, Y., Sept.-Oct. 05, pp. 472-477.

Investment

driving the $5 billion innovation engine at Intel, Wagner, K., Mar.–Apr. 05, pp. 170-180.

IP networks

Aetheral NoC, concepts, archit. and implement., Goosens, K., Sept.-Oct. 05, pp. 414-421.

Tangram, virtual integration of IP components in a distributed cosimulation environ., de Mello, B.A., Sept.-Oct. 05, pp. 462-471.

Land mobile radio cellular systems

innovation, future depends, May-June 05, pp. 268-279.

Leakage currents

parametric yield under power and perform. constraints, modeling and anal., Rao, R.R., July-Aug. 05, pp. 376-385.

Lithography

IC design-manufacture interface, thoughts, Wong, A.K., May-June 05, pp. 206-213.

Logic,
see Logic design
Logic arrays,
see Programmable logic arrays
Logic circuits

advanced computer systs., soft errors, Baumann, R., May-June 05, pp. 258-266.

Logic circuit testing

nanoelectronics, hardware-redundant, fault-tolerant logic, Han, J., July-Aug. 05, pp. 328-339.

nanoscale era, recursive TMR, scaling fault tolerance, Thaker, D.D., July-Aug. 05, pp. 298-305.

parametric yield under power and perform. constraints, modeling and anal., Rao, R.R., July-Aug. 05, pp. 376-385.

periodic sq. wave test sig., detect crosstalk faults, Wu, M. S. Mar.–Apr. 05, pp. 160-169.

soft-spot anal., targeting cpd. noise effects, nanometer ccts., Zhao, C., July-Aug. 05, pp. 362-375.

value-added defect testing techs., Jahangiri, J., May-June 05, pp. 224-231.

yield and manufacturability, test paradigms, Madge, R., May-June 05, pp. 240-246.

Logic design

nanoscale era, recursive TMR, scaling fault tolerance, Thaker, D.D., July-Aug. 05, pp. 298-305.

nanotechnologies, reconfiguration-based defect-tolerant design paradigm, He, C., July-Aug. 05, pp. 316-326.

seq.-equivalence verification, principles, Mneimneh, M.N., May-June 05, pp. 248-257.

Logic devices,
see Logic circuits
Low-power electronics

book review; Low Voltage, Low Power VLSI Subsystems (Kiat-Seng Yeo and Roy, K.; 2004), Sapatnekar, S., May-June 05, pp. 280-281.

Management

driving the $5 billion innovation engine at Intel, Wagner, K., Mar.–Apr. 05, pp. 170-180.

Management,
see Outsourcing
Manufacturing systems

new designs for manufacturability (special section), May-June 05, pp. 200-246.

new designs for manufacturability (special section intro.), Carballo, J.-A., May-June 05, pp. 200-205.

Markov processes

nanoelectronics, hardware-redundant, fault-tolerant logic, Han, J., July-Aug. 05, pp. 328-339.

Measurement

IC outlier identification using multiple test metrics, Sabade, S.S., Nov.-Dec. 05, pp. 586-595.

Memories

optimizing RS codes, improve fault tolerance, memories, automatic tech., Neuberger, G., Jan.-Feb. 05, pp. 50-58.

Memory architecture

architectural design of multimedia multiprocessor SoCs, methodology, Lv, T., Jan.-Feb. 05, pp. 18-26.

Memory management

reconfigurable comput. systs., seamless hardware-software integrat., Vuletid, M., Mar.–Apr. 05, pp. 102-113.

Microcomputers

B#, batt. emulator and power-profiling instrum., Park, C., Mar.–Apr. 05, pp. 150-159.

Microprocessor chips,
see Digital signal processing chips
Microprocessors

architectural design of multimedia multiprocessor SoCs, methodology, Lv, T., Jan.-Feb. 05, pp. 18-26.

BEE2, high-end reconfigurable comput. syst., Chang, C., Mar.–Apr. 05, pp. 114-125.

scalable processor instruction set extension, Becker, J., Mar.–Apr. 05, pp. 136-148.

Minimization methods

crosstalk impact minimization, ECC, Rossi, D., July-Aug. 05, pp. 340-348.

Mobile communication

wireless mobile devices, energy-aware distrib. speech recogn., Delaney, B., Jan.-Feb. 05, pp. 39-49.

Molecular electronics

tolerating highly defective fab., 7 strategies, DeHon, A., July-Aug. 05, pp. 306-315.

Monolithic integrated circuits

successful BEOL yield ramp, transfer, mfg., DFM charactn., 65 nm and below, infrastructure, Yeric, G., May-June 05, pp. 232-239.

Monolithic integrated circuits,
see Application specific integrated circuits
MOS integrated circuits,
see CMOS integrated circuits
Multimedia communication

reconfig. manager for dynamically reconfig. hardware, Resano, J., Sept.-Oct. 05, pp. 452-461.

Multimedia systems

architectural design of multimedia multiprocessor SoCs, methodology, Lv, T., Jan.-Feb. 05, pp. 18-26.

high-perform., reconfigurable, embedded multimedia systs., software develop., La Rosa, A., Jan.-Feb. 05, pp. 28-38.

keeping current, Si and systs. technol., mid-90s, Wagner, K., Jan.-Feb. 05, pp. 7-9.

Multimedia systems,
see Multimedia communication
Multiplying circuits

optimizing RS codes, improve fault tolerance, memories, automatic tech., Neuberger, G., Jan.-Feb. 05, pp. 50-58.

Multiprocessing

architectural design of multimedia multiprocessor SoCs, methodology, Lv, T., Jan.-Feb. 05, pp. 18-26.

Multiprocessing systems,
see Shared memory systems
Nanotechnology

advanced technologies and reliable design for nanotechnology systems (special section), July-Aug. 05, pp. 295-339.

advanced technologies and reliable design for nanotechnology systems (special section intro.), Bahar, R.I., July-Aug. 05, pp. 295-297.

nanoscale era, recursive TMR, scaling fault tolerance, Thaker, D.D., July-Aug. 05, pp. 298-305.

nanotechnologies, reconfiguration-based defect-tolerant design paradigm, He, C., July-Aug. 05, pp. 316-326.

soft-spot anal., targeting cpd. noise effects, nanometer ccts., Zhao, C., July-Aug. 05, pp. 362-375.

tolerating highly defective fab., 7 strategies. DeHon, A., July-Aug. 05, pp. 306-315.

Network interfaces

wireless mobile devices, energy-aware distrib. speech recogn., Delaney, B., Jan.-Feb. 05, pp. 39-49.

Network routing

placement and routing in 3D integrated circuits, Ababei, C., Nov.-Dec. 05, pp. 520-531.

Networks (circuits),
see Integrated circuits, Multiplying circuits
Network synthesis,
see Integrated circuit design
Numerical analysis,
see Error analysis
Operations research,
see Scheduling
Optimizing compilers

precis, usercentric word-length optim. tool, Chang, M.L., July-Aug. 05, pp. 349-361.

Outsourcing

perspectives on outsourcing (special section), Jan.-Feb. 05, pp. 10-16.

Patents

reexamine patent policies for standards, Berman, V., Jan.-Feb. 05, pp. 71-73.

Pattern recognition,
see Speech recognition
Performance evaluation

Aetheral NoC, concepts, archit. and implement., Goosens, K., Sept.-Oct. 05, pp. 414-421.

analysis and implement. of practical, cost-effective NoCs, Lee, S.-J., Sept.-Oct. 05, pp. 422-433.

bridging the processor-memory performance gap with 3-D IC technol., Liu, C.C., Nov.-Dec. 05, pp. 556-564.

demystifying 3D ICs, pros and cons of going vertical, Davis, W.R., Nov.-Dec. 05, pp. 498-510.

first-order performance prediction of cache memory with wafer-level 3D integration, Zeng, Y., Nov.-Dec. 05, pp. 548-555.

Personnel

truth, outsourcing, Rodgers, T., Jan.-Feb. 05, pp. 12-13.

US, engng., viable profession, Unger, S.H., Jan.-Feb. 05, pp. 10-11.

Pipeline processing

scalable processor instruction set extension, Becker, J., Mar.–Apr. 05, pp. 136-148.

Power supplies to apparatus,
see Computer power supplies
Prediction theory

predicting 3D processor memory chip stack performance, Jacob, P., Nov.-Dec. 05, pp. 540-547.

Program compilers

reconfigurable archit. template, archit. exploration, Mei, B., Mar.–Apr. 05, pp. 90-101.

Program compilers,
see Optimizing compilers
Program interpreters

precis, usercentric word-length optim. tool, Chang, M.L., July-Aug. 05, pp. 349-361.

Programmable circuits,
see Programmable logic arrays
Programmable logic arrays

configurable computing, fabric and systems (special section), Mar.–Apr. 05, pp. 85-125.

configurable computing, fabric and systems (special section intro.), Lysaght, P., Mar.–Apr. 05, pp. 85-89.

Programmable logic arrays,
see Field programmable gate arrays
Programmable logic devices,
see Programmable logic arrays
Programming,
see Functional programming
Program processors

predicting 3D processor memory chip stack performance, Jacob, P., Nov.-Dec. 05, pp. 540-547.

Program processors,
see Program compilers, Program interpreters
Program verification

book review; Comprehensive Functional Verification (Goss, J.C. and Roesner, W.; 05), Martin, G., Sept.-Oct. 05, pp. 478-479.

IEEE P1647, e system verification language, Berman, V., Sept.-Oct. 05, pp. 484-486.

Project engineering,
see Scheduling
Pulse circuits,
see Logic circuits
Random-access storage,
see DRAM chips, SRAM chips
Real time systems

architectural design of multimedia multiprocessor SoCs, methodology, Lv, T., Jan.-Feb. 05, pp. 18-26.

BEE2, high-end reconfigurable comput. syst., Chang, C., Mar.–Apr. 05, pp. 114-125.

reconfig. manager for dynamically reconfig. hardware, Resano, J., Sept.-Oct. 05, pp. 452-461.

Reconfigurable architectures

archit. template, archit. exploration, Mei, B., Mar.–Apr. 05, pp. 90-101.

BEE2, high-end reconfigurable comput. syst., Chang, C., Mar.–Apr. 05, pp. 114-125.

comput. systs., seamless hardware-software integrat., Vuletid, M., Mar.–Apr. 05, pp. 102-113.

configurable computing, fabric and systems (special section), Mar.–Apr. 05, pp. 85-125.

configurable computing, fabric and systems (special section intro.), Lysaght, P., Mar.–Apr. 05, pp. 85-89.

dynamic interconnection of reconfig. modules on reconfig. devices, Bobda, C., Sept.-Oct. 05, pp. 443-451.

high-perform., reconfigurable, embedded multimedia systs., software develop., La Rosa, A., Jan.-Feb. 05, pp. 28-38.

nanotechnologies, reconfiguration-based defect-tolerant design paradigm. He, C., July-Aug. 05, pp. 316-326.

reconfig. manager for dynamically reconfig. hardware, Resano, J., Sept.-Oct. 05, pp. 452-461.

scalable processor instruction set extension, Becker, J., Mar.–Apr. 05, pp. 136-148.

Reduced instruction set computing

high-perform., reconfigurable, embedded multimedia systs., software develop., La Rosa, A., Jan.-Feb. 05, pp. 28-38.

scalable processor instruction set extension, Becker, J., Mar.–Apr. 05, pp. 136-148.

Redundancy

crosstalk impact minimization, ECC, Rossi, D., July-Aug. 05, pp. 340-348.

minimize crosstalk impact, exploiting ECC redundancy, Rossi, D., Jan.-Feb. 05, pp. 59-70.

nanoelectronics, hardware-redundant, fault-tolerant logic, Han, J., July-Aug. 05, pp. 328-339.

nanoscale era, recursive TMR, scaling fault tolerance, Thaker, D.D., July-Aug. 05, pp. 298-305.

nanotechnologies, reconfiguration-based defect-tolerant design paradigm, He, C., July-Aug. 05, pp. 316-326.

tolerating highly defective fab., 7 strategies, DeHon, A., July-Aug. 05, pp. 306-315.

Redundant number systems

precis, usercentric word-length optim. tool, Chang, M.L., July-Aug. 05, pp. 349-361.

Reed-Solomon codes

optimizing RS codes, improve fault tolerance, memories, automatic tech., Neuberger, G., Jan.-Feb. 05, pp. 50-58.

Reliability,
see Fault tolerance, Fault tolerant computing
Research and development

driving the $5 billion innovation engine at Intel, Wagner, K., Mar.–Apr. 05, pp. 170-180.

Research and development management,
see Innovation management
Research initiatives

driving the $5 billion innovation engine at Intel, Wagner, K., Mar.–Apr. 05, pp. 170-180.

Risk analysis

inventions, a result of risk-taking, diversity, and holistic thinking, Zorian, Y., Sept.-Oct. 05, pp. 472-477.

Scheduling

yield-driven, false-path-aware clock skew sched., Tsai, J.-L., May-June 05, pp. 214-222.

Self-testing

periodic sq. wave test sig., detect crosstalk faults, Wu, M. S. Mar.–Apr. 05, pp. 160-169.

Semiconductor device fabrication

test soln. selection, multiple-objective decision models and anals., Hamling, D.T., Mar.–Apr. 05, pp. 126-134.

yield-driven, false-path-aware clock skew sched., Tsai, J.-L., May-June 05, pp. 214-222.

Semiconductor device manufacture

new designs for manufacturability (special section), May-June 05, pp. 200-246.

new designs for manufacturability (special section intro.).,Carballo, J.-A., May-June 05, pp. 200-205.

Semiconductor storage,
see Integrated memory circuits
Sequential logic circuits

seq.-equivalence verification, principles, Mneimneh, M.N., May-June 05, pp. 248-257.

Shared memory systems

bridging the processor-memory performance gap with 3-D IC technol., Liu, C.C., Nov.-Dec. 05, pp. 556-564.

Shift registers

periodic sq. wave test sig., detect crosstalk faults, Wu, M. S., Mar.–Apr. 05, pp. 160-169.

Signal processing,
see Digital signal processing chips
Software engineering

high-perform., reconfigurable, embedded multimedia systs., software develop., La Rosa, A., Jan.-Feb. 05, pp. 28-38.

Software requirements and specifications

keeping current, Si and systs. technol., mid-90s, Wagner, K., Jan.-Feb. 05, pp. 7-9.

seq.-equivalence verification, principles, Mneimneh, M.N., May-June 05, pp. 248-257.

Special issues and sections

advanced technologies and reliable design for nanotechnology systems (special section), July-Aug. 05, pp. 295-339.

advanced technologies and reliable design for nanotechnology systems (special section intro.), Bahar, R.I., July-Aug. 05, pp. 295-297.

configurable computing, fabric and systems (special section), Mar.–Apr. 05, pp. 85-125.

configurable computing, fabric and systems (special section intro.), Lysaght, P., Mar.–Apr. 05, pp. 85-89.

networks on chips (special section), Sept.-Oct. 05, pp. 399-451.

networks on chips (special section intro.), Ivanov, A., Sept.-Oct. 05, pp. 399-403.

new designs for manufacturability (special section), May-June 05, pp. 200-246.

new designs for manufacturability (special section intro.), Carballo, J.-A., May-June 05, pp. 200-205.

perspectives on outsourcing (special section), Jan.-Feb. 05, pp. 10-16.

Speech recognition

wireless mobile devices, energy-aware distrib. speech recogn., Delaney, B., Jan.-Feb. 05, pp. 39-49.

SPICE

soft-spot anal., targeting cpd. noise effects, nanometer ccts., Zhao, C., July-Aug. 05, pp. 362-375.

SRAM chips

advanced computer systs., soft errors, Baumann, R., May-June 05, pp. 258-266.

Standards

reexamine patent policies for standards, Berman, V., Jan.-Feb. 05, pp. 71-73.

sharing standards work with Japan, Berman, V., Mar.–Apr. 05, pp. 182-183.

Standards,
see IEEE standards
Stochastic processes,
see Markov processes
Switching circuits,
see Logic circuits
Synchronization

analysis and implement. of practical, cost-effective NoCs, Lee, S.-J., Sept.-Oct. 05, pp. 422-433.

System-on-chip

Aetheral NoC, concepts, archit. and implement., Goosens, K., Sept.-Oct. 05, pp. 414-421.

analysis and implement. of practical, cost-effective NoCs, Lee, S.-J., Sept.-Oct. 05, pp. 422-433.

book review; Interconnect-Centric Design for Advanced DoC and NoC (Nurmi, J. et al., eds.; 2004), Martin, G., Mar.–Apr. 05, pp. 184-185.

design, synthesis, and test of networks on chips, Pande, P.P., Sept.-Oct. 05, pp. 404-413.

networks on chips (special section), Sept.-Oct. 05, pp. 399-451.

networks on chips (special section intro.), Ivanov, A., Sept.-Oct. 05, pp. 399-403.

physical design for 3D system-on-package, Lim, S. K., Nov.-Dec. 05, pp. 532-539.

Systems software,
see Program processors
Telecommunication,
see Mobile communication, Multimedia communication
Test equipment,
see Automatic test equipment
Testing

IC outlier identification using multiple test metrics. Sabade, S.S., Nov.-Dec. 05, pp. 586-595.

novel transition fault ATPG to reduce yield loss, Liu, X., Nov.-Dec. 05, pp. 576-584.

X-tolerant test response compaction, Mitra, S., Nov.-Dec. 05, pp. 566-574.

Testing,
see Automatic testing, Built-in self test
Three-dimensional displays

3D chip stack technology using through chip interconnects, Benkart, P., Nov.-Dec. 05, pp. 512-518.

demystifying 3D ICs, pros and cons of going vertical, Davis, W.R., Nov.-Dec. 05, pp. 498-510.

physical design for 3D system-on-package, Lim, S. K., Nov.-Dec. 05, pp. 532-539.

placement and routing in 3D integrated circuits, Ababei, C., Nov.-Dec. 05, pp. 520-531.

predicting 3D processor memory chip stack performance, Jacob, P., Nov.-Dec. 05, pp. 540-547.

User interfaces,
see Graphical user interfaces
Very-large-scale integration

periodic sq. wave test sig., detect crosstalk faults, Wu, M. S., Mar.–Apr. 05, pp. 160-169.

Video cameras

architectural design of multimedia multiprocessor SoCs, methodology, Lv, T., Jan.-Feb. 05, pp. 18-26.

Video coding

architectural design of multimedia multiprocessor SoCs, methodology, Lv, T., Jan.-Feb. 05, pp. 18-26.

Video equipment,
see Video cameras
Video signal processing,
see Video coding
Virtual reality

reconfigurable comput. systs., seamless hardware-software integrat., Vuletid, M., Mar.–Apr. 05, pp. 102-113.

VLSI

book review; Low Voltage, Low Power VLSI Subsystems (Kiat-Seng Yeo and Roy, K.; 2004), Sapatnekar, S., May-June 05, pp. 280-281.

VLSI,
see Wafer-scale integration
Voltage control

book review; Low Voltage, Low Power VLSI Subsystems (Kiat-Seng Yeo and Roy, K.; 2004), Sapatnekar, S., May-June 05, pp. 280-281.

Wafer-scale integration

3D chip stack technology using through chip interconnects, Benkart, P., Nov.-Dec. 05, pp. 512-518.

first-order performance prediction of cache memory with wafer-level 3D integration, Zeng, Y., Nov.-Dec. 05, pp. 548-555.

Yield estimation

parametric yield under power and perform. constraints, modeling and anal., Rao, R.R., July-Aug. 05, pp. 376-385.

successful BEOL yield ramp, transfer, mfg., DFM charactn., 65 nm and below, infrastructure, Yeric, G., May-June 05, pp. 232-239.

value-added defect testing techs., Jahangiri, J., May-June 05, pp. 224-231.

yield and manufacturability, test paradigms, Madge, R., May-June 05, pp. 240-246.

yield-driven, false-path-aware clock skew sched., Tsai, J.-L., May-June 05, pp. 214-222

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