Issue No.06 - November/December (2005 vol.22)
Subhasish Mitra , Intel
Michael Mitzenmacher , Harvard University
Nishant Patil , Intel
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2005.154
Larger, denser designs lead to more defects; higher quality requirements and new test methods lead to an explosion in test data volume. Test compression techniques attempt to do more testing with fewer bits. This article summarizes one such method, X-compact, which addresses how unknowns, the bane of compression and logic BIST techniques, are eliminated.
VLSI Test, Testability, Built-In Test
Subhasish Mitra, Michael Mitzenmacher, Nishant Patil, "X-Tolerant Test Response Compaction", IEEE Design & Test of Computers, vol.22, no. 6, pp. 566-574, November/December 2005, doi:10.1109/MDT.2005.154